DS_FT231X Datasheet, PDF (14/44 Pages) List of Unclassifed Manufacturers – Future Technology Devices International Ltd FT231X

FT231X USB TO FULL HANDSHAKE UART IC
Datasheet
Version 1.2
Document No.: FT_000565 Clearance No.: FTDI# 261
USB Transceiver. The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface
to the USB cable. The output drivers provide +3.3V level slew rate control signalling, whilst a differential
input receiver and two single ended input receivers provide USB data in, Single-Ended-0 (SE0) and USB
reset detection conditions respectfully. This function also incorporates a 1.5kΩ pull up resistor on USBDP.
The block also detects when connected to a USB power supply which will not enumerate the device but
still supply power and may be used for battery charging.
USB DPLL. The USB DPLL cell locks on to the incoming NRZI USB data and generates recovered clock
and data signals for the Serial Interface Engine (SIE) block.
Internal 12MHz Oscillator – The Internal 12MHz Oscillator cell generates a 12MHz reference clock.
This provides an input to the x4 Clock Multiplier function. The 12MHz Oscillator is also used as the
reference clock for the SIE, USB Protocol Engine and UART FIFO controller blocks.
Clock Multiplier / Divider. The Clock Multiplier / Divider takes the 12MHz input from the Internal
Oscillator function and generates the 48MHz, 24MHz, 12MHz and 6MHz reference clock signals. The 48Mz
clock reference is used by the USB DPLL and the Baud Rate Generator blocks.
Serial Interface Engine (SIE). The Serial Interface Engine (SIE) block performs the parallel to serial
and serial to parallel conversion of the USB data. In accordance with the USB 2.0 specification, it
performs bit stuffing/un-stuffing and CRC5/CRC16 generation. It also verifies the CRC on the USB data
stream.
USB Protocol Engine. The USB Protocol Engine manages the data stream from the device USB control
endpoint. It handles the low level USB protocol requests generated by the USB host controller and the
commands for controlling the functional parameters of the UART in accordance with the USB 2.0
specification chapter 9.
FIFO RX Buffer (512 bytes). Data sent from the USB host controller to the UART via the USB data OUT
endpoint is stored in the FIFO RX (receive) buffer. Data is removed from the buffer to the UART transmit
register under control of the UART FIFO controller. (Rx relative to the USB interface).
FIFO TX Buffer (512 bytes). Data from the UART receive register is stored in the TX buffer. The USB
host controller removes data from the FIFO TX Buffer by sending a USB request for data from the device
data IN endpoint. (Tx relative to the USB interface).
UART FIFO Controller. The UART FIFO controller handles the transfer of data between the FIFO RX and
TX buffers and the UART transmit and receive registers.
UART Controller with Programmable Signal Inversion and High Drive. Together with the UART
FIFO Controller the UART Controller handles the transfer of data between the FIFO RX and FIFO TX
buffers and the UART transmit and receive registers. It performs asynchronous 7 or 8 bit parallel to serial
and serial to parallel conversion of the data on the RS232 (or RS422 or RS485) interface.
Control signals supported by UART mode include RTS, CTS, DSR, DTR, DCD and RI. The UART Controller
also provides a transmitter enable control signal pin option (TXDEN) to assist with interfacing to RS485
transceivers. RTS/CTS, DSR/DTR and XON / XOFF handshaking options are also supported. Handshaking
is handled in hardware to ensure fast response times. The UART interface also supports the RS232
BREAK setting and detection conditions.
Additionally, the UART signals can each be individually inverted and have a configurable high drive
strength capability. Both these features are configurable in the MTP memory.
Baud Rate Generator – The Baud Rate Generator provides a 16x clock input to the UART Controller
from the 48MHz reference clock. It consists of a 14 bit pre-scalar and 3 register bits which provide fine
tuning of the baud rate (used to divide by a number plus a fraction or “sub-integer”). This determines the
baud rate of the UART, which is programmable from 183 baud to 3 Mbaud.
The FT231X supports all standard baud rates and non-standard baud rates from 183 Baud up to 3
Mbaud. Achievable non-standard baud rates are calculated as follows –
Baud Rate = 3000000 / (n + x)
where ‘n’ can be any integer between 2 and 16,384 ( = 2¹⁴ ) and ‘x’ can be a sub-integer of the value 0,
0.125, 0.25, 0.375, 0.5, 0.625, 0.75, or 0.875. When n = 1, x = 0, i.e. baud rate divisors with values
between 1 and 2 are not possible.
This gives achievable baud rates in the range 183.1 baud to 3,000,000 baud. When a non-standard baud
rate is required simply pass the required baud rate value to the driver as normal, and the FTDI driver will
calculate the required divisor, and set the baud rate. See FTDI application note AN232B-05 on the FTDI
website (www.ftdichip.com) for more details.
Copyright © 2013 Future Technology Devices International Limited
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