PS20251 Datasheet, PDF (12/25 Pages) List of Unclassifed Manufacturers – Dual COFDM demodulator with PID filters and MRC diversity

PS20251
3.2 Automatic Gain Control
An AGC module compares the absolute value of the digitized signal with a programmable reference.
The error signal is filtered and is used to control the gain of the amplifier. A sigma-delta modulated
output is provided, which has to be RC low-pass filtered to obtain the voltage to control the amplifier.
The bandwidth of the AGC is set to a large value for quick acquisition then reduced to a small value
for tracking.
The AGC is free running during OFDM channel changes and locks to the new channel while the tuner
lock is being established. This is one of the features of PS20251 used to minimize acquisition time. A
robust AGC lock mechanism is provided and the other parts of the PS20251 begin to acquire only after
the AGC has locked.
3.3 IF to Baseband Conversion
Sampling a 36.17 MHz IF signal at 45 MHz results in a spectrally inverted OFDM signal centred at
approximately 8.9 MHz. The first step of the demodulation process is to convert this signal to a complex
(in-phase and quadrature) signal in baseband. A correction for spectral inversion is implemented during
this conversion process. Note also that the PS20251 has control mechanisms to search automatically for
an unknown spectral inversion status.
3.4 Adjacent Channel Filtering
Adjacent channels, in particular the Nicam digital sound signal associated with analogue channels,
are filtered prior to the FFT.
3.5 Interpolation and Clock Synchronisation
PS20251 uses digital timing recovery and this eliminates the need for an external VCXO. The ADC
samples the signal at a fixed rate, for example, 45.0 MHz. Conversion of the 45.0 MHz signal to the OFDM
sample rate is achieved using the time-varying interpolator. The OFDM sample rate is 64/7 MHz for 8 MHz
and this is scaled by factors 6/8 and 7/8 for 6 and 7 MHz channel bandwidths. The nominal ratio of the
ADC to OFDM sample rate is programmed in a PS20251 register (defaults are for 45 MHz sampling and 8
MHz OFDM). The clock recovery phase locked loop in the PS20251 compensates for inaccuracies in this
ratio due to uncertainties of the frequency of the sampling clock.
3.6 Carrier Frequency Synchronisation
There can be frequency offsets in the signal at the input to OFDM, partly due to tuner step size and
partly due to broadcast frequency shifts, typically 1/6 MHz. These are tracked out digitally, up to 1 MHz
in 2 K and 8 K modes, without the need for an analogue frequency control (AFC) loop.
The default frequency capture range has been set to ±286 kHz in the 2 K and 8 K mode. However, these
values can be increased, if necessary, by programming an on-chip register (CAPT_RANGE). It is
recommended that a larger capture range be used for channel scan in order to find channels with
broadcast frequency shifts, without having to adjust the tuner. After the OFDM module has locked (the
AFC will have been previously disabled), the frequency offset can be read from an on-chip register.
3.7 Symbol Timing Synchronisation
This module computes the optimum sample position to trigger the FFT in order to eliminate or minimize
inter-symbol interference in the presence of multi-path distortion. Furthermore, this trigger point is
continuously updated to dynamically adapt to time-variations in the transmission channel.
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