PS20251 Datasheet, PDF (11/25 Pages) List of Unclassifed Manufacturers – Dual COFDM demodulator with PID filters and MRC diversity

PS20251
Figure 5 FEC block diagram
HP/LP
stream from
OFDM
Pre-Vierbi
BER
Viterbi
decoder
BER monitor
MPEG frame
aligner
De-
interleaver
Reed-Solomon
decoder
Descrambler
PC
Uncorrected
block count
UBC monitor
Post-Vierbi
BER
BER monitor
The FSM controller shown in Figure 4 controls both the demodulator and the FEC. The controller
facilitates the automated search of all parameters or any sub-set of parameters of the received signal. This
mechanism provides the fast channel scan and acquisition performance, whilst requiring minimal software
overhead in the host driver.
The algorithms and architectures used in the PS20251 have been optimized to minimize
power consumption.
3.1 Analogue-to-Digital Converter
The PS20251 has a high performance 10-bit analogue-to-digital converter (ADC) which can sample a 6, 7
or 8 MHz bandwidth OFDM signal, with its spectrum centered at:
• 36.17 MHz IF
• 43.75 MHz IF
• 5 - 10 MHz near-zero IF
An on-chip programmable phase locked loop (PLL) is used to generate the ADC sampling clock. The PLL
is highly programmable allowing a wide choice of sampling frequencies to suit any IF frequency, and all
signal bandwidths.
PLESSEY SEMICONDUCTORS LTD
TAMERTON ROAD | ROBOROUGH | PLYMOUTH | DEVON | PL6 7BQ
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