KSZ8463MLI-EVAL Datasheet, PDF (10/16 Pages) List of Unclassifed Manufacturers – KSZ8463ML/RL Evaluation Board User Guide

KSZ8463_eval_bd_user_guide_1.1.docx
As shown in Table 4 and Table 5, JP28 is used for enabling or disabling the generation of 50MHz
reference clock from the REFCLK_O pin of the KSZ8463RL/FRL. The 50MHz reference clock is always
provided to KSZ8463RL/FRL via REFCLK_I (pin 27).
JUMPER
FUNCTION
SETTING
JP28
50 MHz Reference
clock generation
Pins 1-2 closed: REFCLK_O is enabled
(EN_REFCLKO pin = 1)
Pins 2-3 closed: REFCLK_O is disabled
(EN_REFCLKO pin = 0)
Table 4 MII Port Configuration Settings
DEFAULT
(no jumper)
REFCLK_O
disabled
JP28 Setting
(EN_REFCLKO pin)
Pins 2-3 closed
(EN_REFCLKO = 0,
REFCLK_O is off)
Pins 1-2 closed
(EN_REFCLKO = 1,
REFCLK_O is on)
Clock Source
Note
External 50MHz Ref Clock from oscillator X1/X2 25MHz clock is not
(or J4 pin 9) is input to REFCLK_I.
used.
REFCLK_O output must connect to
X1/X2 25MHz clock is
REFCLK_I, and also drives to J4 pin 12. required.
Table 5 RMII Clock Setting
The RMII provided by the KSZ8463RL/FRL is connected to the device’s third MAC. It complies with the
RMII Specification. The following table describes the signals used by the RMII interface. Refer to RMII
Specification for full detail on the signal description.
RMII
Signal
Name
REFCLK
CRS_DV
RXD0
RXD1
TX_EN
TXD0
TXD1
RMII
Signal Description
Synchronous 50 MHz clock
reference for receive, transmit
and control interface
Carrier sense/
Receive data valid
Receive data bit 0
Receive data bit 1
Transmit enable
Transmit data bit 0
Transmit data bit 1
RX_ER Receive error
Pin number
on MII
connectors
12
8
7
6
13
14
15
10
Direction (with
respect to the
PHY)
Input
Output
Output
Output
Input
Input
Input
Output
Direction (with
respect to the
MAC)
Input or Output
Input
Input
Input
Output
Output
Output
Input or not required
Test
Points
TP5
TP6
TP4
TP11
TP6
TP7
TP16
TP15
Table 6 RMII Signal Description
Micrel, Inc.
Confidential
10/16
July 17, 2013
Rev. 1.1