CPCI-7300 Datasheet, PDF (1/2 Pages) List of Unclassifed Manufacturers – 80 MB/s High-Speed 32-CH Digital I/O Cards

PCI/PCIe-7300A, cPCI-7300
80 MB/s High-Speed 32-CH Digital I/O Cards
CompactPCI
Introduction
PCI-7300A
ADLINK's PCI/PCIe-7300A and cPCI-7300 are ultra-highspeed digital I/O card consisting of 32 digital input/output channels. High
performance designs and state-of-the-art technology make these cards ideal for a wide range of applications, such as high-speed data
transfer, digital pattern generation and digital pattern capture applications, and logic analyzer applications. Trigger signals are available
to start the data acquisition of pattern generation.
■ Maximum Data Acquisition Rate
For sustained data transfer directly from or to host memory, the maximum data acquisition rate can be 80 MB/s. The maximum data
transfer rates between external device and onboard FIFO can be up to 80 MB/s for DO and 160 MB/s for DI. 80MB/s is achieved by
32-bit data width multiplied by an internal 20 MHz clock. 160 MB/s is achieved by 32-bit data width with an external 40 MHz clock
for digital input channels only. The PCI/PCIe-7300A, cPCI-7300 can reach 160 MB/s throughput only when the acquired data length
is less than FIFO size (16 k samples).
PCIe-7300A
■ Bus Mastering DMA
The PCI/PCIe-7300A, cPCI-7300 performs high-speed data transfers between onboard FIFO and host memory using bus mastering
DMA and scatter gather. When the PCI/PCIe-7300A, cPCI-7300 becomes the bus master, it takes control of the PCI/PCIe/cPCI bus,
transfers data at burst speed, and then releases the bus. The host memory can be utilized as much as possible to store data when the
data acquisition throughput is less than the sustained PCI bus bandwidth.
cPCI-7300
■ Scatter Gather Support
For bus master devices, the hardware has the special-design built-in support for transferring data to and from non-contiguous ranges
of physical memory. The PCI/PCIe-7300A, cPCI-7300 contains multiple pairs of address and length registers, each one describing
a single contiguous buffer segment. This allows the PCI/PCIe-7300A, cPCI-7300 to perform I/O using buffers that are scattered
throughout DMA address space. These multiple address and count registers are often referred to as a scatter/gather list, and you can
also think of these bus masters as having their own built-in mapping registers. With scatter gather support, the data transfer size is no
longer a limitation, and moreover, ring buffer is easily achieved with the link list of the scattered memory.
Features
■ x1 lane PCI Express^® Interface (PCIe-7300A)
■ Supports a 32-bit 5 V PCI bus (PCI-7300A)
■ 3U Eurocard form factor, CompactPCI compliant
(PICMG 2.0 R2.1) (cPCI-7300)
■ 32-CH 5 V/TTL digital inputs/outputs
■ 20 MHz (80 MB/s) maximum transfer rate
■ 8, 16, or 32-bit transfers
■ I/O Port Configurations
The PCI/PCIe-7300A, cPCI-7300 is initially configured as two ports: PORT A and PORT B. Each port controls 16 digital I/O lines.
The I/O ports can be configured as either input or output. According to outside device environment, the PCI/PCIe-7300A, cPCI-7300 can
be configured to meet all high-speed digital I/O data transferring. PCI/PCIe-7300A, cPCI-7300 can support many different digital I/O
operation modes:
■ Internal clock: The digital input and output operations are handled by internal clock and data is transferred by busmastering DMA.
■ External clock: The digital input and output operations are handled by external In/Out strobe signals (DI_REQ or DO_ACK)
and data is transferred by busmastering DMA.
■ 4 auxiliary DI & 4 auxiliary DO
■ Onboard 64 kB FIFO
■ Onboard programmable timer pacer clock
■ _{Timed digital input sampling controlled by internal}
■ Handshaking: Through REQ and ACK signals, the digital I/O data can have simple handshaking data transfer to guarantee no data loss.
■ Pattern generation: The PCI/PCIe-7300A, cPCI-7300 reads or writes digital data at a prede termined rate. Users can control the rate
internally via by onboard counters with 50 ns timing resolution.
Words
FIFO
Words
Words
FIFO
timer or ex_Dt₃e₁rn_..a₁l c₆loc_Lk_{ocal Bus}
■ IndReEpGendent trigger signals to start data
acquisition and pattern generation
■ Sca_Rt_Ete_Gr-ga^Dth¹e⁵r^.D^.0MA
■
Supports
h_Dan₁d₅s_.h_.0aking
digital^PI^C/O^I/Pt^Cr^Ia^ensfer
Controller
mode
■ ReRpeEaGted digital pattern generation from FIFO
■ Active terminators for high-speed and longdistance
dat_Ra_Et_Grans^Dfe³r^{1..1 6}
Data FIFO
DI
Fragmented
Scatter Gather Physical Memory
Timer
PCI Bus
Controller
DO
Retrieves
Data
CPU
REG
■ Operating_DS₃y_.s_.0tems
8254
REG
• Window_Ds ₇7_./_.V₄ista/XP/2000/2T0i0m3eSr erver
• Linux
G
C_■on_R&ter_co_ol_{mmended Software}
Timing
• AD-Logger
Block Diagram of PCI-7300A
PCI/PCIe Bus
• VB.NET/VC.NET/VB/VC++/BCB/Delphi
• DAQBench
■ Driver Support
• DAQPilot for LabVIEW™
• PCIS-DASK for Windows
• PCIS-DASK/X for Linux
Port A (16DIO)
REG
Active
Terminators
Port B (16DIO)
REG
REG
Active
Terminators
REG
AUX DO 3..0
AUX DI 3..0
DITRIG,DIREQ
DIACK
DOTRIG,DOACK
DOREQ
16K Words
FIFO
16K Words
16K Words
FIFO
D31..1 6 _{Local Bus}
REG
D15..0
REG
D15..0
REG
PCI/PCIe
Controller
D31..1 6
REG
REG
D3..0
REG
D7..4
Control
REG
&
Timing
Block Diagram of PCI-7300A
8254
Timer
PCI/PCIe Bus
Data FIFO
DI
Fragmented
Scatter Gather Physical Me
Timer
PCI Bus
Controller
DO
Retrieves
Data
CPU
2-41 _{www.adlinktech.com}