CS18LV02565 Datasheet, PDF (9/14 Pages) List of Unclassifed Manufacturers – HIGH SPEED SUPER LOW POWER SRAM

READ CYCLE2 ^(1,3,4)
High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
READ CYCLE3 ^(1,4)
ADDRESS
OE
CE
D_OUT
t_RC
t_AA
t_OLZ
t_CLZ(5)
t_OE
t_CE
t_OH
t_OHZ(1,5)
t_CHZ(5)
NOTES:
1. /WE is high in read Cycle.
2. Device is continuously selected when /CE = V_IL.
3. Address valid prior to or coincident with CE transition low.
4. /OE = VIL.
5. Test conditions assume signal transition times of 5ns or less, timing reference levels of 0.5VCC, input
pulse levels of 0V to VCC and output loading specified in Figure 1A.
6. Transition is measured ±500mV from steady state with C_L = 5pF as shown in Figure 1B. The parameter is
guaranteed but not 100% tested.
9
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.