CS18LV02565 Datasheet, PDF (4/14 Pages) List of Unclassifed Manufacturers – HIGH SPEED SUPER LOW POWER SRAM

High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
PIN DESCRIPTIONS
Name Type
Function
A0 – A14 Input Address inputs for selecting one of the 32,768 x 8 bit words in the RAM
/CE is active LOW. Chip enable must be active when data read from or write
to the device. If chip enable is not active, the device is deselected and in a
/CE
Input
standby power mode. The DQ pins will be in high impedance state when the
device is deselected.
The Write enable input is active LOW. It controls read and write operations.
With the chip selected, when /WE is HIGH and /OE is LOW, output data will
/WE
Input
be present on the DQ pins, when /WE is LOW, the data present on the DQ
pins will be written into the selected memory location.
The output enable input is active LOW. If the output enable is active while the
chip is selected and the write enable is inactive, data will be present on the
/OE
Input
DQ pins and they will be enabled. The DQ pins will be in the high impedance
state when /OE is inactive.
DQ0~DQ7
These 8 bi-directional ports are used to read data from or write data into the
I/O
RAM.
Vcc
Power Power Supply
Gnd
Power Ground
TRUTH TABLE
Mode
/CE /WE
/OE
Standby
H
X
X
Output Disabled
L
H
H
Read
L
H
L
Write
L
L
X
DQ0~7
High Z
High Z
D_OUT
D_IN
Vcc Current
I_CCSB, I_CCSB1
I_CC
I_CC
I_CC
4
Rev. 2.0
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