BC41B143A-DS-001PE Datasheet, PDF (82/102 Pages) List of Unclassifed Manufacturers – BlueCpre 4-ROM Single Chip Bluetooth v2.0 System with EDR

Device Terminal Descriptions
10.7.11 PCM Configuration
The PCM configuration is set using two PS Keys, PSKEY_PCM_CONFIG32 and
PSKEY_PCM_LOW_JITTER_CONFIG. The following tables detail these PS Keys. PSKEY_PCM_CONFIG32.
The default for this key is 0x00800000 i.e. first slot following sync is active, 13-bit linear voice format, long frame
sync and interface master generating 256kHz PCM_CLK from 4MHz internal clock with no tri-stating of
PCM_OUT. PSKEY_PCM_LOW_JITTER_CONFIG is described in Table 10.12.
Name
Bit Position Description
-
SLAVE_MODE_EN
SHORT_SYNC_EN
-
SIGN_EXTEND_EN
LSB_FIRST_EN
TX_TRISTATE_EN
TX_TRISTATE_RISING_EDGE_EN
SYNC_SUPPRESS_EN
GCI_MODE_EN
MUTE_EN
48M_PCM_CLK_GEN_EN
LONG_LENGTH_SYNC_EN
-
MASTER_CLK_RATE
ACTIVE_SLOT
SAMPLE_FORMAT
0
1
2
3
4
5
6
7
8
9
10
11
12
[20:16]
[22:21]
[26:23]
[28:27]
Set to 0.
0 selects Master mode with internal generation of
PCM_CLK and PCM_SYNC. 1 selects Slave mode
requiring externally generated PCM_CLK and
PCM_SYNC. This should be set to 1 if
48M_PCM_CLK_GEN_EN (bit 11) is set.
0 selects long frame sync (rising edge indicates start of
frame), 1 selects short frame sync (falling edge indicates
start of frame).
Set to 0.
0 selects padding of 8 or 13-bit voice sample into a 16-
bit slot by inserting extra LSBs, 1 selects sign extension.
When padding is selected with 13-bit voice sample, the
3 padding bits are the audio gain setting; with 8-bit
samples the 8 padding bits are zeroes.
0 transmits and receives voice samples MSB first, 1
uses LSB first.
0 drives PCM_OUT continuously, 1 tri-states PCM_OUT
immediately after the falling edge of PCM_CLK in the
last bit of an active slot, assuming the next slot is not
active.
0 tristates PCM_OUT immediately after the falling edge
of PCM_CLK in the last bit of an active slot, assuming
the next slot is also not active. 1 tristates PCM_OUT
after the rising edge of PCM_CLK.
0 enables PCM_SYNC output when master, 1
suppresses PCM_SYNC whilst keeping PCM_CLK
running. Some CODECS utilise this to enter a low power
state.
1 enables GCI mode.
1 forces PCM_OUT to 0.
0 sets PCM_CLK and PCM_SYNC generation via DDS
from internal 4 MHz clock, as for BlueCore4-ROM. 1
sets PCM_CLK and PCM_SYNC generation via DDS
from internal 48 MHz clock.
0 sets PCM_SYNC length to 8 PCM_CLK cycles and 1
sets length to 16 PCM_CLK cycles. Only applies for long
frame sync and with 48M_PCM_CLK_GEN_EN set to 1.
Set to 0b00000.
Selects 128 (0b01), 256 (0b00), 512 (0b10) kHz
PCM_CLK frequency when master and
48M_PCM_CLK_GEN_EN (bit 11) is low.
Default is ‘0001’. Ignored by firmware.
Selects between 13 (0b00), 16 (0b01), 8 (0b10) bit
sample with 16 cycle slot duration or 8 (0b11) bit sample
with 8 cycle slot duration.
Table 10.11: PSKEY_PCM_CONFIG32 Description
BC41B143A-ds-001Pe
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