BC41B143A-DS-001PE Datasheet, PDF (81/102 Pages) List of Unclassifed Manufacturers – BlueCpre 4-ROM Single Chip Bluetooth v2.0 System with EDR

Device Terminal Descriptions
10.7.10 PCM_CLK and PCM_SYNC Generation
BlueCore4-ROM has two methods of generating PCM_CLK and PCM_SYNC in master mode. The first is
generating these signals by Direct Digital Synthesis (DDS) from BlueCore4-ROM internal 4MHz clock. Using this
mode limits PCM_CLK to 128, 256 or 512kHz and PCM_SYNC to 8kHz. The second is generating PCM_CLK
and PCM_SYNC by DDS from an internal 48MHz clock which allows a greater range of frequencies to be
generated with low jitter but consumes more power. This second method is selected by setting bit
‘48M_PCM_CLK_GEN_EN’ in PSKEY_PCM_CONFIG32. When in this mode and with long frame sync, the
length of PCM_SYNC can be either 8 or 16 cycles of PCM_CLK, determined by ‘LONG_LENGTH_SYNC_EN’ in
PSKEY_PCM_CONFIG32.
The Equation 10.10 describes PCM_CLK frequency when being generated using the internal 48MHz clock:
f = ^{CNT _ RATE} × 24MHz
CNT _ LIMIT
Equation 10.10: PCM_CLK Frequency When Being Generated Using the Internal 48MHz clock
The frequency of PCM_SYNC relative to PCM_CLK can be set using following equation:
f = ^{PCM _ CLK}
SYNC _ LIMIT × 8
Equation 10.11: PCM_SYNC Frequency Relative to PCM_CLK
CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_LOW_JITTER_CONFIG. As an
example, to generate PCM_CLK at 512kHz with PCM_SYNC at 8kHz, set
PSKEY_PCM_LOW_JITTER_CONFIG to 0x08080177.
BC41B143A-ds-001Pe
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