MDT10C23 Datasheet, PDF (8/19 Pages) List of Unclassifed Manufacturers – Fully CMOS static design, 8-bit data bus,On chip ROM size : 2 K words

(B) Program Memory
MDT10C23
Address
000- 7FF
7FF
Description
Program memory
The starting address of the power on, external reset or WDT
8. Reset Condition for all Registers
Register
Address
Power-On Reset
/MCLR Reset
CPIO A
1111 1111
1111 1111
CPIO B
1111 1111
1111 1111
TMR
--11 1111
--11 1111
IAR
00h
RTCC
01h
xxxx xxxx
uuuu uuuu
PC
02h
1111 1111
1111 1111
STATUS
03h
0001 1xxx
000# #uuu
MSR
04h
100x xxxx
100u uuuu
PORT A
05h
xxxx xxxx
uuuuuuuu
PORT B
06h
xxxx xxxx
uuuu uuuu
CMR
07h
0000 0000
uuuu uuuu
Note : u unchanged, x unknown, - unimplemented, read as “0”
# value depends on the condition of the following table
WDT Reset
1111 1111
1111 1111
--11 1111
uuuu uuuu
1111 1111
000# #uuu
1uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Condition
/MCLR reset (not during SLEEP)
/MCLR reset during SLEEP
WDT reset (not during SLEEP)
WDT reset during SLEEP
9. Instruction Set
Status: bit 4
U
1
0
0
Status: bit 3
u
0
1
0
Instruction Code
010000 00000000
010000 00000001
010000 00000010
Mnemonic
Operands
NOP
Function
No operation
CLRWT
Clear Watchdog timer
SLEEP
Sleep mode
Operating
None
0 WT
0 WT, stop OSC
Status
TF, PF
TF, PF
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 8
2004/7 Ver. 1.1