IDT77V012 Datasheet, PDF (8/46 Pages) List of Unclassifed Manufacturers – Data Path Interface to UTOPIA Level 1 Header Translation Device

IDT77V012
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The 77V012 uses a UTOPIA level 1 interface to receive and transmit
ATM cells to and from the PHY device. It has a UTOPIA master interface
and operates with a 8-bit data bus. UTOPIA cell level handshake is used
to transfer the cells between the ATM layer and the PHY layer. UTOPIA
byte level handshake is not supported by the 77V012.
The Data Path Interface (DPI) uses a 4-bit data bus, which interfaces
the 77V012 to the IDT SwitchStar.
The EEPROM holds information for initialization and Discovery/Iden-
tify cells. The EEPROM is an option and does not need to be imple-
mented.
The Utility Bus interface contains the control pins used to program
and read the internal PHY registers.
The SRAM interface is used to configure internal registers at reset
and to interface with the external SRAM during normal operation.
The Misc. interface offers two test pins, that are controlled through
registers.
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The 77V012 offers a fully compliant UTOPIA Level 1 Receive inter-
face, as specified by the UTOPIA Level 1 specification. The interface is
a UTOPIA master that operates with a 8-bit Input Data Bus
(RxDATA[7:0]). UTOPIA cell level handshake is used to receive ATM
cells from the PHY device. The other signals associated with this inter-
face are Receive Start of Cell (RSOC), Receive Enable (RENB),
Receive Cell Available (RCLAV), Receive LED (RxLED), and Receive
Clock (RCLK).
RCLK is a continuous clock, which is half the frequency of System
Clock (SYSCLK).
RxLED indicates if there is activity on the UTOPIA receive bus. This
open drain signal asserts low when a cell is transferred over the bus,
and will stay asserted for 2²² RCLK cycles. At 40MHz this is approxi-
mately 0.1 seconds.
The 77V012 will assert RENB low upon detection of a high RCLAV.
Once RSOC is detected the 77V012 will receive the entire cell without
interruption.
When a TAG is not being used there is no delay between back to
back cells. There is a maximum delay of eight clock cycles between
back to back cells when a four byte TAG is being used.
DPI
Receive
Interface
DRxCLK
DRxFRM
DRxDATA[3:0]
DPI
Transmit
Interface
DTxCLK
DTxFRM
DTxDATA[3:0]
Serial
EEPROM
Interface
System
Interface
Utility Bus
Interface
EEDIN
EEDOUT
EECS
EECLK
SYSRST
SYSCLK
PHYCS
ALE
RD
WR
PHYRST
PHYINT
AD[7:0]
IDT77V012
RCLK
RSOC
RENB
RxDATA[7:0]
RCLAV
RxLED
TCLK
TSOC
TENB
TxDATA[7:0]
TCLAV
TxPRTY
TxLED
ADDR[17:0]
DATA[31:0]
SCLK
ADSP
GW
CE
OE
CNTRL_A
CNTRL_B
UTOPIA
Receive
Interface
UTOPIA
Transmit
Interface
SRAM
Interface
Misc.
Interface
Figure 2 77V012 Interfaces
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March 26, 2001