IDT77V012 Datasheet, PDF (1/46 Pages) List of Unclassifed Manufacturers – Data Path Interface to UTOPIA Level 1 Header Translation Device

Data Path Interface (DPI) to
UTOPIA Level 1 Header
Translation Device
IDT77V012
)HDWXUHV /LVW
‹ _{8, 12, 24, 28 or 32-bit ATM header lookup. Ideal for network}
side of SwitchStar DSLAM designs where full header access
is needed
‹ _{Supports VPI Tunneling}
‹ _{Supports both UNI and NNI formats}
‹ _{Accounting functionality counts the number of cells on a}
per VC basis
‹ _{8-bit UTOPIA Level 1 Tx and Rx interfaces}
‹ _{Supports UTOPIA Level 1 cell mode operation}
‹ _{4-bit DPI Tx and Rx interfaces}
‹ _{DPI interface supports cell sizes from 52 to 56 bytes for}
applications requiring a TAG
‹ _{DPI interface operates up to 66MHz}
‹ _{In-Stream™ (In-band) programming for configuration of the}
77V012, PHY and external search SRAM
‹ _{Supports up to 8K active connections with an external 128K}
x 32 SRAM. Up to 16K connections are supported in a 256K
x 32 SRAM
‹ _{Inserts new ATM cell header and up to four bytes of TAG in}
receive direction, and removes TAG from cell header in
transmit direction
%ORFN 'LDJUDP
‹ _{Utility bus interface for programming PHY devices}
‹ _{Single +3.3V ± 0.3V power supply required}
‹ _{Inputs are +5.0V tolerant}
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The IDT77V012 provides full header translation functionality along
with Data Path Interface (DPI) to UTOPIA Level 1 translation for switch
and DSLAM designs using the IDT SwitchStar. The address search and
replacement algorithm is performed using a VPI Tunneling or Full
Header format on 8, 12, 24, 28 or 32-bits of the header. This added flex-
ibility makes it suitable for both UNI and NNI formats. External memory
is required to perform the header translation (receive direction only),
which will support up to 16K connections using a 256K x 32 SRAM. The
new header, which is obtained as a result of the search, can be used to
overwrite the existing cell header in the receive path. A four byte TAG
can also be added to aid in routing cells.
The 77V012 also contains cell counters in the transmit and receive
direction. The counters can be used to provide detailed per VC
accounting information for a particular port.
Other features include In-Stream™ programming, which can be
utilized on either the DPI or UTOPIA interfaces, a Utility Bus interface for
accessing registers in the PHY device, and an interface for an
EEPROM.
SRAM
64K x 32
to
256K x 32
OC-3
or
STS-3
IDT77155
PHY
UTOPIA 1
Receive
UTOPIA 1
Transmit
Utility
Bus
IDT77V012
UTOPIA 1
to DPI
interface w/
Header
Translation
DPI
Receive
DPI
Transmit
IDT77V400
Switching
Memory
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5347drw01
Figure 1 Typical IDT77V012 Application with the IDT77V400 Switching Memory
 2001 Integrated Device Technology, Inc.
1 of 46
March 26, 2001
DSC 5347/7