IC41C16105 Datasheet, PDF (8/18 Pages) List of Unclassifed Manufacturers – 1M X 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE

IC41C16105
IC41LV16105
AC CHARACTERISTICS (Continued)^{(1,2,3,4,5,6)}
(Recommended Operating Conditions unless otherwise noted.)
Symbol
tACH
tOEH
tDS
tDH
tRWC
tRWD
tCWD
tAWD
tPC
tRASP
tCPA
tPRWC
tCOH
tO..
tWHZ
tCLCH
tCSR
tCHR
tORD
tRE.
tT
Parameter
Column-Address Setup Time to CAS
Precharge during WRITE Cycle
OE Hold Time from WE during
READ-MODI.Y-WRITE cycle⁽¹⁸⁾
Data-In Setup Time^{(15, 22)}
Data-In Hold Time^{(15, 22)}
READ-MODI.Y-WRITE Cycle Time
RAS to WE Delay Time during
READ-MODI.Y-WRITE Cycle⁽¹⁴⁾
CAS to WE Delay Time^{(14, 20)}
Column-Address to WE Delay Time⁽¹⁴⁾
.ast Page Mode READ or WRITE
Cycle Time⁽²⁴⁾
RAS Pulse Width
Access Time from CAS Precharge⁽¹⁵⁾
READ-WRITE Cycle Time⁽²⁴⁾
Data Output Hold after CAS LOW
Output Buffer Turn-Off Delay from
CAS or RAS^{(13,15,19, 29)}
Output Disable Delay from WE
Last CAS going LOW to .irst CAS
returning HIGH⁽²³⁾
CAS Setup Time (CBR RE.RESH)^{(30, 20)}
CAS Hold Time (CBR RE.RESH)^{(30, 21)}
OE Setup Time prior to RAS during
HIDDEN RE.RESH Cycle
Auto Refresh Period (1,024 Cycles)
Transition Time (Rise or .all)^{(2, 3)}
-50
Min. Max.
15 —
8
—
0
—
8
—
108 —
64 —
26 —
39 —
20 —
50 100K
— 30
56 —
5
—
1.6 12
3
10
10 —
5
—
8
—
0
—
— 16
1
50
-60
Min. Max.
15 —
10 —
0
—
10 —
133 —
77 —
32 —
47 —
25 —
60 100K
— 35
68 —
5
—
1.6 15
3
10
10 —
5
—
10 —
0
—
— 16
1
50
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 p. (Vcc = 5.0V ±10%)
One TTL Load and 50 p. (Vcc = 3.3V ±10%)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V ±10%);
VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V ±10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V ±10%, 3.3V ±10%)
S2-8
Integrated Circuit Solution Inc.
DR014-0A 06/07/2001