BC41B143A-DS-003PC Datasheet, PDF (71/94 Pages) List of Unclassifed Manufacturers – BlueCore 4-ROM Plug-n-Go Single Chip Bluetooth v2.0 + EDR System

Device Terminal Descriptions
10.7.8 PCM Timing Information
Symbol
Parameter
Min
Typ
Max
Unit
4MHz DDS
128
generation. Selection
of frequency is
-
256
-
kHz
programmable. See
Table 10.10.
512
48MHz DDS
f_mclk
PCM_CLK frequency ^{generation. Selection}
of frequency is
programmable. See
Table 10.11 and
2.9
PCM_CLK and
PCM_SYNC
Generation on page
75.
-
kHz
-
t_mclkh(a)
t_mclkl(a)
-
PCM_SYNC frequency
-
8
PCM_CLK high
4MHz DDS generation 980
-
PCM_CLK low
4MHz DDS generation 730
-
PCM_CLK jitter
48MHz DDS
generation
kHz
-
ns
ns
21
ns pk-pk
t_dmclksynch
Delay time from PCM_CLK high to PCM_SYNC
high
-
-
20
ns
t_dmclkpout
Delay time from PCM_CLK high to valid
PCM_OUT
-
-
20
ns
t_dmclklsyncl
Delay time from PCM_CLK low to PCM_SYNC
low (Long Frame Sync only)
-
-
20
ns
t_dmclkhsyncl
Delay time from PCM_CLK high to PCM_SYNC
low
-
-
20
ns
t_dmclklpoutz
Delay time from PCM_CLK low to PCM_OUT
high impedance
-
-
20
ns
t_dmclkhpoutz
Delay time from PCM_CLK high to PCM_OUT
high impedance
-
-
20
ns
t_supinclkl
Set-up time for PCM_IN valid to PCM_CLK low
30
-
t_hpinclkl
Hold time for PCM_CLK low to PCM_IN invalid
10
-
-
ns
-
ns
Table 10.8: PCM Master Timing
(a) _{Assumes normal system clock operation. Figures will vary during low power modes, when system clock speeds are}
reduced.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
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