SI5320 Datasheet, PDF (7/34 Pages) List of Unclassifed Manufacturers – SONET/SDH PRECISION CLOCK MULTIPLIER IC

Si5320
Table 3. AC Characteristics
(V_DD33 = 3.3 V ±5%, T_A = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Input Clock Frequency (CLKIN)
FEC[1:0] = 00 (non FEC)
INFRQSEL[2:0] = 001
INFRQSEL[2:0] = 010
INFRQSEL[2:0] = 011
INFRQSEL[2:0] = 100
INFRQSEL[2:0] = 101
INFRQSEL[2:0] = 110
f_CLKIN
No FEC Scaling
19.436 — 21.685 MHz
38.872 — 43.369
77.744 — 86.738
155.48 — 173.48
310.97 — 346.95
621.95 — 693.90
Input Clock Frequency (CLKIN)
FEC[1:0] = 01 (forward FEC)
INFRQSEL[2:0] = 001
INFRQSEL[2:0] = 010
INFRQSEL[2:0] = 011
INFRQSEL[2:0] = 100
INFRQSEL[2:0] = 101
INFRQSEL[2:0] = 110
f_CLKIN
255/238 FEC Scaling
18.142 — 20.239 MHz
36.284 — 40.478
72.568 — 80.955
145.13 — 161.91
290.27 — 323.82
580.54 — 647.64
Input Clock Frequency (CLKIN)
FEC[1:0] = 10 (reverse FEC)
INFRQSEL[2:0] = 001
INFRQSEL[2:0] = 010
INFRQSEL[2:0] = 011
INFRQSEL[2:0] = 100
INFRQSEL[2:0] = 101
INFRQSEL[2:0] = 110
f_CLKIN
238/255 FEC Scaling
20.826 — 23.234 MHz
41.652 — 46.465
83.305 — 92.934
166.61 — 185.87
333.22 — 371.74
666.44 — 743.47
Input Clock Rise Time (CLKIN)
Input Clock Fall Time (CLKIN)
Input Clock Duty Cycle
CLKOUT Frequency Range^*
FRQSEL[1:0] = 00 (no output)
FRQSEL[1:0] = 01
FRQSEL[1:0] = 10
FRQSEL[1:0] = 11
CLKOUT Rise Time
t_R
t_F
C_{DUTY_IN}
Figure 2
Figure 2
—
—
11
ns
—
—
11
ns
40
50
60
%
f_{O_19}
f_{O_155}
f_{O_622}
—
—
—
19.436 — 21.685 MHz
155.48 — 173.48
621.95 ^— 693.90
t_R
Figure 2; single-ended; after —
213 260 ps
3 cm of 50 Ω FR4 stripline
CLKOUT Fall Time
t_F
Figure 2; single-ended; after —
191 260 ps
3 cm of 50 Ω FR4 stripline
Output Clock Duty Cycle
C_{DUTY_OUT}
Differential:
48
—
52
%
(CLKOUT+) – (CLKOUT–)
RSTN/CAL Pulse Width
t_RSTN
20
—
—
ns
*Note: The Si5320 provides a 1/32, 1/16, 1/8, 1/4, 1/2, 1, 2, 4, 8, 16, or 32x clock frequency multiplication function with an
option for additional frequency scaling by a factor of 255/238 or 238/255 for FEC rate compatibility.
Rev. 2.3
7