SI5320 Datasheet, PDF (16/34 Pages) List of Unclassifed Manufacturers – SONET/SDH PRECISION CLOCK MULTIPLIER IC

Si5320
2. Functional Description
The Si5320 is a high-performance precision clock
multiplication and clock generation device. This device
accepts a clock input in the 19, 38, 77, 155, 311, or
622 MHz range, attenuates significant amounts of jitter,
and multiplies the input clock frequency to generate a
clock output in the 19, 155, or 622 MHz range.
Additional optional scaling by a factor of either 255/238
(15/14) or 238/255 (14/15) is provided for compatibility
with systems that provide or require clocks that are
scaled for forward error correction (FEC) rates. Typical
applications for the Si5320 in SONET/SDH systems
would be the generation and/or cleaning of 19.44,
155.52, or 622.08 MHz clocks from 19.44, 38.88, 77.76,
155.52, 311.04, or 622.08 MHz clock sources.
The Si5320 employs Silicon Laboratories DSPLL^™
technology to provide excellent jitter performance while
minimizing the external component count and
maximizing flexibility and ease-of-use. The Si5320’s
DSPLL phase locks to the input clock signal, attenuates
jitter, and multiplies the clock frequency to generate the
device’s SONET/SDH-compliant clock output. The
DSPLL loop bandwidth is user-selectable, allowing the
Si5320’s jitter performance to be optimized for different
applications. The Si5320 can produce a clock output
with jitter generation as low as 0.3 ps_RMS (see Table 4),
making the device an ideal solution for clock
multiplication in SONET/SDH (including OC-48 and OC-
192) and Gigabit Ethernet systems.
The Si5320 monitors the clock input signal for loss-of-
signal, and provides a loss-of-signal (LOS) alarm when
missing pulses are detected. The Si5320 provides a
digital hold capability to continue generation of a stable
output clock when the input reference is lost.
2.1. DSPLL^™
The Si5320’s phase-locked loop (PLL) uses Silicon
Laboratories' DSPLL technology to eliminate jitter,
noise, and the need for external loop filter components
found in traditional PLL implementations. This is
achieved by using a digital signal processing (DSP)
algorithm to replace the loop filter commonly found in
analog PLL designs. This algorithm processes the
phase detector error term and generates a digital
control value to adjust the frequency of the voltage-
controlled oscillator (VCO). The technology produces
low phase noise clocks with less jitter than is generated
using traditional methods. See Figure 4 for an example
phase noise plot. In addition, because external loop
filter components are not required, sensitive noise entry
points are eliminated, making the DSPLL less
susceptible to board-level noise sources.
This digital technology also allows for highly-stable and
consistent operation over all process, temperature, and
voltage variations. The benefits are smaller, lower
power, cleaner, more reliable, and easier-to-use clock
circuits.
2.1.1. Selectable Loop Filter Bandwidth
The digital nature of the DSPLL loop filter allows control
of the loop filter parameters without the need to change
external components. The Si5320 provides the user
with up to eight user-selectable loop bandwidth settings
for different system requirements. The base loop
bandwidth is selected using the BWSEL [1:0] along with
DBLBW = 0 pins. When DBLBW is driven high, the
bandwidth selected on the BWSEL[1:0] pins is doubled.
(See Table 7.)
When DBLBW is asserted, the Si5320 shows improved
jitter generation performance. DBLBW function is
defined only when hitless recovery and FEC scaling are
disabled. Therefore, when DBLBW is high, the user
must also drive FXDDELAY high and FEC[1:0] to 00 for
proper operation.
2.2. Clock Input and Output Rate Selection
The Si5320 provides a 1/32x, 1/16x, 1/8x, 1/4x, 1/2x,
1x, 2x, 4x, 8x, 16x, or 32x clock frequency multiplication
function with an option for additional frequency scaling
by a factor of 255/238 or 238/255 for FEC rate
compatibility. Output rates vary in accordance with the
input clock rate. The multiplication factor is configured
by selecting the input and output clock frequency
ranges for the device.
The Si5320 accepts an input clock in the 19, 38, 77,
155, 311, or 622 MHz frequency range. The input
frequency range is selected using the INFRQSEL[2:0]
pins. The INFRQSEL[2:0] settings and associated
output clock rates are given in Table 8.
The Si5320’s DSPLL phase locks to the clock input
signal to generate an internal VCO frequency that is a
multiple of the input clock frequency. The internal VCO
frequency is divided down to produce a clock output in
the 19, 155, or 622 MHz frequency range. The clock
output range is selected using the Frequency Select
(FRQSEL[1:0]) pins. The FRQSEL[1:0] settings and
associated output clock rates are given in Table 9.
The Si5320 clock input frequencies are variable within
the range specified in Table 3 on page 7. The output
rates scale accordingly. When a 19.44 MHz input clock
is used with no FEC scaling enabled, the clock output
frequency is 19.44, 155.52, or 622.08 MHz.
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Rev. 2.3