VMX1C1016 Datasheet, PDF (65/76 Pages) List of Unclassifed Manufacturers – Versa Mix 8051 Mixed-Signal MCU

VMX51C1016
The respective values of the IP1.x and IP0.x bits
define the priority level of the interrupt group vs.
the other interrupt groups as follows:
TABLE 118: INTERRUPT PRIORITY LEVEL
IP1.x
IP0.x
0
0
0
1
1
0
1
1
Priority Level
Level 0 (Low)
Level 1
Level 2
Level 3 (High)
The WDTSTAT bit of the IP0 register is the
watchdog status flag, which is set to 1 by the
hardware whenever a watchdog timer overflow
occurs. This bit must be cleared manually.
Finally, bit 7 of the IP0 register can be used as a
general purpose user flag.
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