NT256S72V89A0G Datasheet, PDF (6/12 Pages) List of Unclassifed Manufacturers – 32Mx72 bit One Bank Unbuffered SDRAM Module

NT256S72V89A0G
256MB : 32M x 72
Unbuffered SDRAM Module
Operating, Standby, and Refresh Currents (TA =0 to 70 °C , VDD =3.3 ± 0.3V)
Parameter
Symbol
Test condition
Operating current
I_CC1
Precharge
standby current
in power-down mode
I_CC2P
I_CC2PS
Precharge
standby current in non
power-down mode
ICC2N
ICC2NS
No Operating current
( Active state : 4 bank)
ICC3P
ICC3N
Operating current
( Burst mode )
I_CC4
Auto(CBR)
refresh current
I_CC5
Self refresh current
I_CC6
Serial PD Device
I_SB
Standby Current
1 bank operation , tRC = tRC(mim), tCK = min
Active-Precharge Command cycling
without burst operation
CKE0 ≤ VIL (max), tCK = min,
S0 , S2 = V_IH (min)
CKE0 ≤ VIL (max), tCK =oo,
S0 , S2 = V_IH (min)
CKE0 ≥ VIH (min), tCK = min
S0 , S2 = V_IH (min)
CKE0 ≥ VIH (min), tCK =oo,
S0 , S2 = V_IH (min)
CKE0 ≤ VIL (max), tCK =min.
S0 , S2 = V_IH (min) (Power Down Mode)
CKE0 ≥ VIH (min), tCK =min
S0 , S2 = V_IH (min)
tCK =min , Read/ Write command cycling,
Multiple banks active, gapless data, BL=4
t_CK =min, CBR command cycling
CKE0 ≤ 0.2V
V_IN = GND or V_DD
Speed
- 7K - 75B - 8B
Unit
Note
1170 1080 1035
mA
1, 2
16
16
16
mA
16
16
16
mA
270
270
180
mA
3
72
72
72
mA
4
54
54
54
mA
5
540
540
360
mA
3
1080 1080
810
mA
2, 6
1575 1575 1395
mA
27
27
27
mA
30
30
30
µA
7
Serial PD Device Active
Power Supply Current
ICCA
SCL Clock Frequency=100 MHz
1
1
1
µA
8
1. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t CK and t RC . Input
signals are changed up to three times during t RC (min).
2. The specified values are obtained with the output open.
3. Input signals are changed once during three clock cycles.
4. Input signals are stable.
5. Active standby current will be higher if Clock Suspend is entered during a Burst Read cycle (add 1mA per DQ).
6. Input signals are changed once during t ck(min) .
7. VDD =3.3V
8. Input pulse levels VDD x 0.1 to VDD x 0.9, input rise and fall times 10ns, input and output timing levels VDD x 0.5, output load 1 TTL gate and
CL=100pF.
Preliminary 09 / 2001
6
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.