NT256S72V89A0G Datasheet, PDF (10/12 Pages) List of Unclassifed Manufacturers – 32Mx72 bit One Bank Unbuffered SDRAM Module

NT256S72V89A0G
256MB : 32M x 72
Unbuffered SDRAM Module
Serial Presence Detect -- Part 1 of 2
32Mx72 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 3.3v SDRAMs with SPD
Byte
Description
SPD Entry Value
-7K
-75B
-8B
0 Number of Serial PD Bytes Written during Production
128
1 Total Number of Bytes in Serial PD device
256
2 Fundamental Memory Type
SDRAM
3 Number of Row Addresses on Assembly
13
4 Number of Column Addresses on Assembly
10
5 Number of DIMM Bank
1
6. Data Width of Assembly
X72
7 Data Width of Assembly (cont’)
X72
8 Voltage Interface Level of this Assembly
LVTTL
9 SDRAM Device Cycle Time at CL=3
7ns 7.5ns 8ns
10 SDRAM Device Access Time from Clock at CL=3
5.4ns 5.4ns 6ns
11 DIMM Configuration Type
ECC
12 Refresh Rate/Type
SR/1x(7.8us)
13 Primary SDRAM Width
X8
14 Error Checking SDRAM Device Width
X8
15 SDRAM Device Attributes: Min CLk Delay, Random Col Access
1 Clock
16 SDRAM Device Attributes: Burst Length Supported
1,2,4,8
SDRAM Device Attributes:
17
4
Number of Device Banks
18 SDRAM Device Attributes: CAS Latencies Supported
2/3
2/3
2/3
19 SDRAM Device Attributes: CS Latency
0
20 SDRAM Device Attributes: WE Latency
0
21 SDRAM Device Attributes
Unbuffered
Wr-1/Rd Burst, Precharge All,
22 SDRAM Device Attributes: General
Auto-Precharge, VDD +/-
10%
23 Minimum Clock Cycle at CL=2
7.5ns 10ns 10ns
24 Maximum Data Access Time from Clock at CL=2
5.4ns 6ns
6ns
25 Minimum Clock Cycle Time at CL=1
N/A
26 Maximum Data Access Time from Clock at CL=1
N/A
27 Minimum Row Precharge Time(tRP)
15ns 20ns 20ns
28 Minimum Row Active to Row Active delay (tRRD)
15ns 15ns 20ns
29 Minimum RAS to CAS delay (tRCD)
15ns 20ns 20ns
30 Minimum RAS Pulse Width (tRAS)
45ns 45ns 50ns
31 Module Bank Density
256MB
32 Address and Command Setup Time Before Clock
1.5ns 1.5ns 2ns
33 Address and Command Hold Time After Clock
0.8ns 0.8ns 1ns
34 Data Input Setup Time Before Clock
1.5ns 1.5ns 2ns
35 Data Input Hold Time After Clock
0.8ns 0.8ns 1ns
36-61 Reserved
Undefined
62 SPD Revision
1.2A 1.2A 1.2A
63 Checksum for byte 0 - 62
Checksum Data
Serial PD Data Entry
(Hexadecimal)
-7K
-75
-8B
80
08
04
0D
0A
01
48
00
01
70
75
80
54
54
60
02
82
08
08
01
0F
04
06
06
06
01
01
00
0E
75
A0
A0
54
60
60
00
00
0F
14
14
0F
0F
14
0F
14
14
2D
2D
32
40
15
15
20
08
08
10
15
15
20
08
08
10
00
12
12
12
1E
64
AB
Note
Preliminary 09 / 2001
10
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.