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DDX-2102 Datasheet, PDF (6/17 Pages) List of Unclassifed Manufacturers – All-Digital High Efficiency Power Amplifier
DDX-2102
3.0 DDX-2102 POWER DEVICE
The DDX-2102 Power Device is a dual channel H-Bridge that can deliver more than 65 watts per
channel (<10%THD) of audio output power at very high efficiency. It converts both DDX® and binary-
controlled PWM signals into audio power at the load. It includes a logic interface, integrated bridge
drivers, high efficiency MOSFET outputs, and thermal and short circuit protection circuitry. In DDX®
mode, two logic level signals per channel are used to control high-speed MOSFET switches to connect
the speaker load to the input supply or to ground in a bridge configuration, according to Apogee's
patented damped ternary PWM. In Binary Mode operation, both Full Bridge and Half Bridge Modes are
supported. This device includes over-current and thermal protection as well as under-voltage lockout
with automatic recovery. A thermal warning status is also provided.
INL[1:2]
INR[1:2]
VL
PWRDN
TRI-STATE
Logic I/F
and Decode
Left
H-Bridge
OUTPL
OUTNL
INL[1:2]
INR[1:2]
VL
PWRDN
TRI-STATE
Logic I/F
and Decode
LeftA
½-Bridge
LeftB
½-Bridge
OUTPL
OUTNL
FAULT
TWARN
Protection
Circuitry
Regulators
Right
H-Bridge
OUTPR
OUTNR
Figure 3 - DDX-2102 Block Diagram,
Full- Bridge DDX® or Binary Modes
FAULT
TWARN
Protection
Circuitry
RightA
½-Bridge
OUTPR
Regulators
RightB
½-Bridge
OUTNR
Figure 4 - DDX-2102 Block Diagram,
Binary Half-Bridge Mode
3.1 Logic Interface and Decode
The DDX-2102 power outputs are controlled using one or two logic level timing signals. In order to
provide a proper logic interface, the VL input must operate at the same voltage as the DDX® controller
logic supply. VL (Logic Reference Voltage) is recommended to be powered and stable prior to Vcc
achieving > 7V to assure proper power up sequence. VL is recommended to remain powered and
stable until after Vcc has decayed below 7V during power removal.
3.2 Protection Circuitry
The DDX-2102 includes protection circuitry for over-current and thermal overload conditions. A thermal
warning pin TWARN is activated low (open-drain MOSFET) when the IC temperature exceeds 130°C,
in advance of the thermal shutdown protection. When a fault condition is detected (logical OR of over-
current and thermal), an internal fault signal acts to immediately disable the output power MOSFETs,
placing both H-bridges in a high impedance state. At the same time an open-drain MOSFET connected
to the FAULT pin is switched on.
There are two possible modes subsequent to activating a fault. The first is a SHUTDOWN mode. With
FAULT (pull-up resistor) and TRI-STATE pins independent, an activated fault will disable the device,
signaling low at the FAULT output. The device may subsequently be reset to normal operation by
toggling the TRI-STATE pin from High to Low to High using an external logic signal.
The second is an AUTOMATIC recovery mode. This is depicted in the application circuit in Figure 19.
The FAULT and TRI-STATE pins are shorted together and connected to a time constant circuit
comprising of RT and CT. An activated FAULT will force a reset on the TRI-STATE pin causing normal
operation to resume following a delay determined by the time constant of the circuit. If the fault
condition is still present, the circuit operation will continue repeating until the fault condition is removed.
Specifications are subject to change without notice.
129 Morgan Drive, Norwood, MA 02062
voice: (781) 551-9450
fax: (781) 440-9528
CONTROLLED DOCUMENT: P_903-000055_Rev08 DDX-2102 Data Sheet.doc
email: apogee@apogeeddx.com
DRN: PRELIMINARY Page 6 of 17