BQ4024 Datasheet, PDF (6/12 Pages) List of Unclassifed Manufacturers – 128Kx16 Nonvolatile SRAM

bq4024/bq4024Y
Write Cycle (TA = 0 to 70°C, VCCmin ≤ VCC ≤ VCCmax)
-85
-120
Symbol
Parameter
Min. Max. Min. Max. Units
Conditions/Notes
tWC
Write cycle time
85 - 120 -
ns
tCW
Chip enable to end of write 75 - 100 -
ns
(1)
tAW
Address valid to end of write 75 - 100 -
ns
(1)
tAS
Address setup time
Measured from address valid to be-
0
-
0
-
ns _{ginning of write. (2)}
tWP
Write pulse width
65 - 85 -
Measured from beginning of write to
ns _{end of write. (1)}
tWR1
Write recovery time
(write cycle 1)
Measured from WE going high to end
5
-
5
-
ns _{of write cycle. (3)}
tWR2
Write recovery time
(write cycle 2)
15 - 15 -
Measured from CE going high to end
ns _{of write cycle. (3)}
tDW
Data valid to end of write
35 -
45 -
Measured to first low-to-high transi-
ns _{tion of either CE or WE.}
tDH1
Data hold time
(write cycle 1)
Measured from WE going high to end
0
-
0
-
ns _{of write cycle.(4)]}
tDH2
Data hold time
(write cycle 2)
10 - 10 -
Measured from CE going high to end
ns _{of write cycle. (4)}
Write enabled to output in
tWZ
high-Z
0 30 0 40 ns I/O pins are in output state. (5)
Output active from end of
tOW
write
0
-
0
-
ns I/O pins are in output state. (5)
Notes:
1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later
transition of CE going low and WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.
Sept. 1992
6