GM5115 Datasheet, PDF (50/58 Pages) List of Unclassifed Manufacturers – ONPANEL LCD PANEL CONTROLLER

*** Genesis Microchip Confidential ***
gm5115/25 Preliminary Data Sheet
Pin Name
GPIO0/PWM0
GPIO1/PWM1
GPIO2/PWM2
GPIO3/TIMER1
GPIO4/UART_DI
GPIO5/UARD_D0
GPIO6/TCON_SHC
GPIO7/TCON_TDIV
GPIO8/IRQINn
GPIO9/TCON_ROE2
GPIO10/TCON_ROE3
GPIO11/ROM_WEn
GPIO12/NVRAM_SDA
GPIO13/NVRAM_SCL
GPIO14/DDC_SCL
GPIO15/DDC_SDA
GPIO16/HFSn
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21/IRQn
GPIO22/HCLK
Pin Number
40
41
42
43
44
45
46
47
39
48
49
50
51
52
6
7
205
1
208
207
206
4
204
Alternate function
PWM0, PWM1 and PWM2 back light intensity controls, as described in section 4.18.2 below.
Timer1 input of the OCM.
OCM UART data in/out signals respectively (section 4.15.3 above).
Horizontal timing signals in the TCON column driver interface.
OCM external interrupt source (IRQINn).
Row output enables ROE2 and ROE3 in the TCON row driver interface.
Write enable for external ROM if programmable FLASH device is used (section 4.15.3 above).
Data and clock lines for master 2-wire serial interface to NVRAM when gm5115/25 is used in
standalone configuration (section Figure 26).
Clock and data lines for 2-wire serial interface connected to the Direct Data Channel (DDC) of the DVI
input, for passing HDCP keys (see 4.4.3 above) or for DDC2Bi communication (see 4.15.5 above).
Serial data line for 2-wire host interface or for DDC2Bi communication (see 4.15.5 above).
No alternative function.
OCM interrupt output pin.
Serial input clock for 2-wire host interface or for DDC2Bi communication (see 4.15.5 above).
Table 17. gm5115/25 GPIOs and Alternate Functions
4.16 Bootstrap Configuration Pins
During hardware reset, the external ROM address pins ROM_ADDR[15:0] are configured as
inputs. On the negating edge of RESETn, the value on these pins is latched and stored. This
value is readable by the on-chip microcontroller (or an external microcontroller via the host
interface). Install a 10K pull-up resistor to indicate a ‘1’, otherwise a ‘0’ is indicated because
ROM_ADDR[15:0] have a 60KΩ internal pull-down resistor.
Signal Name
Pin Name
Description
HOST_ADDR(4:0)
USER_BITS(4:0)
HOST_ADDR(5)
HOST_ADDR(6)
HOST_PROTOCOL
HOST_PORT_EN
OCM_START
USER_BITS(7:5)
OSC_SEL
OCM_ROM_CNFG(1)
ROM_ADDR(4:0)
ROM_ADDR5
ROM_ADDR6
ROM_ADDR7
ROM_ADDR8
ROM_ADDR9
ROM_ADDR(12:10)
ROM_ADDR13
ROM_ADDR14
If using 2-wire host protocol, these are bits 4:0 of the serial bus device address.
Otherwise, these settings are available for reading from a status register but are otherwise unused by the
gm5115/25. Used for “soft” configuration settings.
If using 2-wire host protocol, this is bit 5 of serial the bus device address.
Otherwise, program this bit to 0.
If using 2-wire host protocol, this is bit 6 of the serial bus device address.
Otherwise, program this bit to 0.
Program this bit to 0 for 2-wire host protocol operation.
Program this bit to 0 for 2-wire host protocol operation.
Determines the operating condition of the OCM after HW reset:
0 = OCM remains in reset until enabled by register bit.
1 = OCM becomes active after OCM_CLK is stable.
These settings are available for reading from a status register but are otherwise unused by the gm5115/25.
Selects reference clock source:
0 = XTAL and TCLK pins are connected to a crystal oscillator (see Figure 4).
1 = TCLK input is driven with a single-ended TTL/CMOS clock oscillator (see Figure 7).
Together with OCM_CONTROL register (0x22) bit 4, this bit selects internal/external ROM configuration.
0 = All 48K of ROM is internal.
1 = All 48K of ROM is in external ROM using ROM_ADDR15:0 address outputs if
register 0x22 bit 4 is 0. If register 0x22 bit 4 is 1, 0-32K ROM is internal, and
32K~48K ROM is external using ROM_ADDR13:0 address outputs.
Table 18. Bootstrap Signals
June 2002
41
C5115-DAT-01H