GM5115 Datasheet, PDF (25/58 Pages) List of Unclassifed Manufacturers – ONPANEL LCD PANEL CONTROLLER

*** Genesis Microchip Confidential ***
gm5115/25 Preliminary Data Sheet
SCLK
SENSE_ACLK
DVI_CLK
IP_CLK
DCLK
IP_CLK
DP_CLK
SCLK
ACLK
RCLK/2
TCLK
RCLK/4
OCM_CLK
TCLK
Figure 9.
On-chip Clock Domains
IFM_CLK
4.2 Hardware Reset
Hardware Reset is performed by holding the RESETn pin low for a minimum of 1µs. A TCLK
input (see Clock Options above) must be applied during and after the reset. When the reset period
is complete and RESETn is de-asserted, the power-up sequence is as follows:
1. Reset all registers of all types to their default state (this is 00h unless otherwise specified in
the gm5115/25 Register Listing).
2. Force each clock domain into reset. Reset will remain asserted for 64 local clock domain
cycles following the de-assertion of RESETn.
3. Operate the OCM_CLK domain at the TCLK frequency.
4. Preset the RCLK PLL to output ~200MHz clock (assumes 14.3MHz TCLK crystal
frequency).
5. Wait for RCLK PLL to Lock. Then, switch the OCM_CLK domain to operate from the
bootstrap selected clock.
6. If a pull-up resistor is installed on ROM_ADDR9 pin (see Table 18), then the OCM becomes
active as soon as OCM_CLK is stable. Otherwise, the OCM remains in reset until
OCM_CONTROL register (0x22) bit 1 is enabled.
4.3 Analog to Digital Converter (ADC)
The gm5115/25 chip has three ADC’s (analog-to-digital converters), one for each color (red,
green, and blue).
June 2002
16
C5115-DAT-01H