COIC5130A Datasheet, PDF (4/20 Pages) List of Unclassifed Manufacturers – Programmable Reed-Solomon Error Correction Encoder and Decoder

COic5130A Specifications
4
Co^~Optic
• Provides complete error location and correction information
• Flags uncorrectable blocks
• 4.5 to 5.5 volt operation
• -40 to + 85 degrees C operation range (extended range available)
• ISO 9000 certified manufacturing
Decoder Functional Description
The device contains a decoder that will provide ( N, N-r ) Reed-Solomon
forward error correction decoding of blocks of eight bit symbols. The
number of parity symbols (r ) may be from 8 to 20, 0 in Pass Through
Mode, and the number of symbols in a block ( N ) up to 255 . Two par-
ity bytes will be used for each symbol error correction. This device will
provide correction of up to 10 symbol errors ( E ) as long as 2E </= r. It
will provide the number of corrections made in each block. Symbol
errors are processed the same regardless of the number of incorrect bits
in the symbol. Processing latency is the same regardless of the number
of errors, including zero, in a block. The device can decode at data rates
from 0 to 40 million symbols per second ( 320 Mbs ) and two or more
devices can be used together ( see Application Brief for Reed-Solomon
FEC ) to process data at higher rates.
Encoder Initialization
Before operations the device must be initialized to define N, r, P ( the
number of parity symbols that can be used ( decoded ) before a block is
determined uncorrectable ) and to set the block error information
report (status) output. A two step process is used.
Step One: Set the level of OptLn to the desired level and maintain
throughtout all operations. While the binary value of P is held on the P
control bus, Reset and DataEn are held low for at least four symbol clock
cycles and then Reset is brought high and held high for at least two more
symbol clock cycles. At the same time the StatEn line is held high if the
decoder block error information bytes ( status ) output are desired and
low if not. Note that the decoder will output corrected parity bytes in the
space formerly used by parity which are not used by block error infor-
mation (status) bytes. Symbols of any value can be used for this step.
Step Two : With Reset high a normal block processing procedure is used
to set up values of N, r, and k ( N-r ). The Enabln is brought high with
the first data symbol and held high throughout the decoding secession.
Also at the beginning of the block DataEn is brought high at the leading
edge of the first symbol clock pulse and held high while the data sym-
bols are being clocked into the device, that is N-r symbol clock pluses.
DataEn is brought low with the first parity symbol and held low for r
symbol clock cycles while the parity symbols are clocked in. DataEn‚s
going high again marks the end of parity and the start of the next block.
Reset will remain high throughout step 2 and normal use until a new
reset cycle is desired. This step will set up the device timing for all fol-
lowing blocks until the device is reinitialized or an alternate length
block with fewer data symbols ( see Alternate Block Length ) is used. A
regular data block may be used for this step but to prevent possible loss
of data a block using dummy symbols of any value is recommended.
Selecting the value of P
The value of P determines the number of parity bytes that can be used
(decoded) before a block is flagged as uncorrectable. The decoder will
always use all of the parity bytes available to correct a block regardless
of the value of P, which is usually set equal to r (the number of parity
bytes) but P can be less or more than r.
1. If P equals r the device will properly correct all blocks where 2E </=
r and mark all other blocks as uncorrectable. This option is almost
always used.
2. If P is less than r the device will use all of the parity bytes to correct
the block but will mark corrected blocks as uncorrected if P < 2E < r.
In this case the error status bytes must be checked to determine if
correction was actually achieved. This feature can be used to detect
more errors than can be corrected, but must be used with care.
3. If P is more than r normal correction will take place but the device
will not provide uncorrectable block flags and may pass on to the out-
put unflagged uncorrected data blocks . THIS SETTING HAS NO
VALUE AND SHOULD NOT BE USED.
4. If P is more than 20 the decoder will pass all information directly to
the data output without any corrections. THIS SETTING HAS NO
VALUE AND SHOULD NOT BE USED.
The value of P may be changed at any time, but any blocks in process at
the time of the change may not be properly flagged if uncorrectable.
Minimum Block Lengths
Minimum block lengths and latency are a function of the number of
parity bytes used in a code. OptLn must be set at the start of initializa-
tion and held at the correct level throughout operations. The device
must repeat Initialization if OptLn is to be changed
The COic5130A allows three different equations to determine the mini-
mum block lengths.When pin 16 is low and pin 9 LOW or NC the default
equation is Minimum Block Length = 5r + 15 bytes. When pin 9 is held
at High and pin 16 is low level Latency1 is invoked and the minimum
block length equation is changed to (2r + 13) bytes. If pin 16 is high
Latency 2 is invoked and the minimum block length is 3r/2 + 15 regar-
dles of the level of pin 9.
Decoder Latency
The time that is required for the data to flow through the device is called
latency and is measured in symbol clock cycles. The devices can be
operated with any of three latencies, under the control of OpLan1,pin 9
and OpLan2, pin 16. Latencies are a function of the block length and
correction level, but unaffected by error patterns. The default latency
(pin 9 and 16 both low) is equal to 2N + 5r + 33 symbol clock cycles,