COIC5130A Datasheet, PDF (2/20 Pages) List of Unclassifed Manufacturers – Programmable Reed-Solomon Error Correction Encoder and Decoder

COic5130A Specifications
2
Co^~Optic
Encoder Functional Description
The COic5130A contains an encoder that will provide ( N, N-r ) Reed-
Solomon forward error correction encoding of blocks of eight bit sym-
bols. The number of parity symbols ( r ) may be from 0 to 20 , 0 in Pass
Through Mode, and the number of symbols in a block ( N ) from r+1 to
255. At the decoder two parity bytes will be used for each untagged
symbol error correction and one parity byte used for a location identi-
fied error (erasure ) correction. This will provide correction of up to 10
errors ( E ) or up to 20 erasures ( e ) or a combination as long as 2E + e
</= r.
The encoder can encode data at rates from 0 to 40 million symbols per
second ( 320 Mbs ) These devices implement the primitive polynomial
Px = x8+ x4 + x3 + x2 + x0 and the generator polynomial
r-1
G ( x) = II ( x - µ i )
i =0
which are compatible with SMPTE D-1/D-2, ANSI ID1/ID2, MIL- STD-
2179A, DVB, DDS, DAVIC, and DSL standards.
Controls are provided to :
1. tri-state the output data bus
2. disable the input data
3. select the output data source
(input data bus or parity generator)
Encoder Functional Block Diagram
Din (7.0) 1
0
1
Encoder
0
Dout (7.0)
En Out
En Out
T (3.0)
TriEn
Reset
Clock
Control
Rty
Encoder Features
• Supports 8 bit symbol Reed-Solomon codes ( N, N- r ) with
0 < r < 20 and r+1 < N < 255, N= symbols per block including par-
ity, r = number of parity bytes (NOTE: r is often called 2t)
• Encoding rates from 0 to 320 Mbs with 0 to 40 Mhz symbol clock
• Implements SMPTE D-1/D-2 Digital Video Standards, DVBS Digital
Video, ANSI ID-1/ID-2, and Mil -STD-2179A coding polynomials
• Requires only one ( byte ) clock. Input and output data are at one
byte per symbol clock for each the encoder and decoder
• Code provides choice of 0 to 20 parity bytes per block
• Provides Pass Through ( no parity ) mode switching on the fly
• Processing latency of only 3 symbol clocks
• Allows code rate changes on the fly
• ISO 9000 certified manufacturing
• 128-pin metal quad flat pack
• Vdd 4.5 to 5.5 volts operation
• - 40 to + 85 degrees C operation
Encoder Initialization
Before operations the encoder must be initialized to define the number
of parity symbols ( r ).
To initialize the binary value of r/2 ( 0 to 10 ) is placed in TA0 - TA3 (TA0
is least significant ) while Reset and EnlnA are held low for four symbol
clock periods. Reset is then brought and held high for two symbol clock
periods. The inputs on TA0 - TA3 can then be released and the section
can start normal operation.
Any TAx pin that is not used must be held low or connected to ground.
Encoding
To encode a block of symbols the enable in line ( EnlnA) and enable out
line ( EnOutA ) are brought high coincident with the leading edge of
first data symbol clock in a new block and remain high until all of the
data symbols are clocked into the encoder section and k-3 symbols out
onto the Dout bus. There is a processing latency ( delay ) of three clock
cycles between the data in ( DinA ) and the data out ( DoutA.). The data
ready signal ( RdyA ) is EnlnA delayed by three clock cycles.
At the leading edge of the clockA pulse after the last data symbol has
been placed into the encoder, EnlnA and EnOutA are brought low. This
will fill the parity generator will zeros. EnlnA and EnOutA are held low
for ( r ) clock cycles which inputs zeros into the encoder while out-
putting the parity code symbols which are appended to the data sym-
bols to form the output data stream. After at least r clock cycles EnlnA
and EnOutA are brought high to start the next block.
The output data bus ( DoutA ) may be put into a high impedance state
by bringing the TriEnA high. This will not effect the operation of the
encoder except to disable the output bus.
When the input enable ( EnlnA) is low, zeros will be clocked into the
encoder input. This can be used to prevent spurious data from being
encoded.