MX26F128J3 Datasheet, PDF (39/47 Pages) List of Unclassifed Manufacturers – Macronix NBit TM Memory Family 128M [x8/x16] SINGLE 3V PAGE MODE eLiteFlash TM MEMORY

MX26F128J3
AC Characteristics--Write Operations (1,2)
Versions
Symbol
Parameter
tPHWL (tPHEL ) RESET High Recovery to WE(CEX) Going Low
tELWL (tWLEL ) CEX (WE) Low to WE(CEX) Going Low
tWP
Write Pulse Width
tDVWH (tDVEH ) Data Setup to WE(CEX) Going High
tAVWH (tAVEH ) Address Setup to WE(CEX) Going High
tWHEH (tEHWH) CEX (WE) Hold from WE(CEX) High
tWHDX (tEHDX) Data Hold from WE(CEX) High
tWHAX (tEHAX) Address Hold from WE(CEX) High
tWPH
Write Pulse Width High
tVPWH (tVPEH) VPEN Setup to WE(CEX) Going High
tWHGL (tEHGL) Write Recovery before Read
tWHRL (tEHRL) WE(CEX) High to STS Going Low
tQVVL
VPEN Hold from Valid SRD, STS Going High
tWHQV5 (tEHQV5) Set Lock-Bit Time
tWHQV6 (tEHQV6) Clear Block Lock-Bits Time
Notes
3
4
4
5
5
6
3
7
8
3,8,9
4,9
4
Valid for All
Speeds
Unit
Min Max
210
ns
0
ns
70
ns
50
ns
55
ns
0
ns
0
ns
0
ns
30
ns
0
ns
35
ns
500 ns
0
ns
64 75/85 us
0.5
2
sec
NOTES:
CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first
edge of CE0, CE1, or CE2 that disables the device (see Table 2).
1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as
during read-only operations. Refer to AC Characteristics-Read-Only Operations.
2. A write operation can be initiated and terminated with either CE X or WE.
3. Sampled, not 100% tested.
4. Write pulse width (tWP) is defined from CEX or WE going low (whichever goes low last) to CEX or WE going high
(whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH.
5. Refer to Table 4 for valid A IN and D IN for block erase, program, or lock-bit configuration.
6. Write pulse width high (t WPH) is defined from CEX or WE going high (whichever goes high first) to CEX or WE
going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL .
7. For array access, tAVQV is required in addition to tWHGL for any accesses after a write.
8. STS timings are based on STS configured in its RY/BY default mode.
9. VPEN should be held at VPENH until determination of block erase, program, or lock-bit configuration success
(SR.1/3/4/5=0).
P/N:PM0960
REV. 1.1,OCT. 18, 2004
39