MC2400 Datasheet, PDF (39/59 Pages) List of Unclassifed Manufacturers – Navigator Motion Processor

6.2 ISA Bus Interface
A complete, ready-to-use ISA (PC/AT) bus interface circuit has been provided to illustrate Navigator
host interfacing, as well as to make it easier for the customer to build a Navigator development
system.
The interface between the PMD Navigator chipset and the ISA (PC-AT) bus is shown on the
following page.
Comments on Schematic
This interface uses a CPLD and two 74LS245s to buffer the data lines. This interface assumes a base
address is assigned in the address space of A9-A0, 300-400 hex. These addresses are generally
available for prototyping and other system-specific uses without interfering with system assignments.
This interface occupies 16 addresses from XX0 to XXF hex though it does not use all the addresses.
Four select lines are provided allowing the base address to be set from 300 to 3F0 hex for the select
lines SW1-SW4 equal to 0- F respectively. The address assignments used are as follows, where
BADR is the base address, 340 hex for example:
Address
340h
342h
344h
348h
use
read-write data
write command -read status
write command -read status
write reset [Data = don't care]
The base address (BADR) is decoded in the 74LS688. It is combined with SA1, SA2, and SA3,
(BADR+0,2,4) to form HSELN to select the I/O chip and the 245’s. (BADR+2,4) asserts HCMD.
Two addresses are used to be compatible with the first generation products, which used BADR+2 to
write command and BADR+4 to read status.
B+8 and IOW* generate a reset pulse, -RS, for the CP chip. The reset instruction is OR'd with
RESET on the bus to initialize the PMD chipset when the PC is reset.
MC2400 Technical Specifications
39