CC2420 Datasheet, PDF (30/87 Pages) List of Unclassifed Manufacturers – 2.4 GHz IEEE 802.15.4 / ZigBee-ready RF Transceiver

SmartRF ^® CC2420
is that FIFO and RAM access must be
terminated by setting CSn high.
CSn
SI
SO
ADDR
Status
ADDR
Status
-
-
ADDR_TXFIFO DATA_ADDR DATA_ADDR+1 DATA_ADDR+2
DATA_8MSB DATA_8LSB
Status
Status
Status
Status
Command
Strobe
Register
Read
TXFIFO
Write
Figure 10. Multiple SPI Access Example
Microcontroller Interface and Pin Description
When used in a typical system, CC2420 will
interface to a microcontroller. This
microcontroller must be able to:
• Program CC2420 into different modes,
read and write buffered data, and read
back status information via the 4-wire
SPI-bus configuration interface (SI, SO,
SCLK and CSn).
• Interface to the receive and transmit
FIFOs using the FIFO and FIFOP
status pins.
• Interface to the CCA pin for clear
channel assessment.
• Interface to the SFD pin for timing
information (particularly for beaconing
networks).
configuration interface (SI, SO, SCLK and
CSn). SO should be connected to an input
at the microcontroller. SI, SCLK and CSn
must be microcontroller outputs.
Preferably the microcontroller should have
a hardware SPI interface.
The microcontroller pins connected to SI,
SO and SCLK can be shared with other
SPI-interface devices. SO is a high
impedance output as long as CSn is not
activated (active low).
CSn should have an external pull-up
resistor or be set to a high level when the
voltage regulator is turned off in order to
prevent the input from floating. SI and
SCLK should be set to a defined level to
prevent the inputs from floating.
Configuration interface
A CC2420 to microcontroller interface
example is shown in Figure 11. The
microcontroller uses 4 I/O pins for the SPI
Chipcon AS SmartRF^® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09
Page 30 of 87