EP520 Datasheet, PDF (3/3 Pages) List of Unclassifed Manufacturers – EUREKA TECHNOLOGY

Address Mux
The Address Mux takes the input address on ADDR[31:0]
and drives the correct bank address on BA and row or col-
umn address on MADDR.
Control Registers
The user can program the SDRAM controller to support dif-
ferent SDRAM sizes, burst lengths, and SDRAM timing
parameters. The registers are accessed through the control
register access signals, CR_XX (all CR_ signals).
Core Modifications
The SDRAM controller is designed in the XCV50PQ240
device. Cores for other packages can also be supported.
Eureka Technology will contract to modify the core to your
specifications.
Pinout
The pinout of the EP520 core has not been fixed to specific
FPGA I/O, thereby allowing flexibility with a user’s applica-
tion. Signal names are shown in Figure 1 and described in
Table 2.
Verification Methods
Functional simulation has been done using Model Technol-
ogy ModelsimTM 5.4b. Static timing analysis has been
done for all paths using the timing analyzer in Xilinx Foun-
dation Series 2.1i.Recommended Design Experience
The user must be familiar with HDL design methodology as
well as instantiation of Xilinx netlists in a hierarchical design
environment.
Recommended Design
Experience
Users should have a basic knowledge about SDRAM and
decide the target device.
Ordering Information
If you have inquiries or want to license our core, please
contact Eureka Technology directly. Eureka Technology
retains the right to make changes to these specifications at
any time without notice.
Phone : [phone]
Email : [e-mail]
Eureka Technology, Inc.
Table 1: Core Signal Pinout
Signal
ADDR[31:0]
ADS_B
BE_B[7:0]
BLAST_B
CE_B
CLK
CR_ADR[1:0]
CR_ADS_B
CR_DT[31:0]
CR_RDY_B
CR_WR
OE_B
OFR_B
READY_B
RESET_B
T_R_B
WR
BA[1:0]
CAS_B
CS_B[3:0]
DQM[7:0]
MADDR[12:0]
RAS_B
REGE
WE_B
Signal
Direction
Description
Input Address input
Input Address strobe
Input Byte enable
Input Burst last
Input Chip enable
Input System clock
Input Register address
Input Control register access
Input Register data
Output Control register ready
Input Register write
Output Output enable
Output Out of range
Output Ready
Input System reset
Output Transmit/Receive
Input Write enable
Output Bank address
Output Column address select
Output Chip select
Output Data mask
Output Memory address
Output Row address select
Output Register mode select
Output Write enable
Related Information
Xilinx Programmable Logic
For information on Xilinx programmable logic or develop-
ment system software, contact your local Xilinx sales office,
or:
Xilinx, Inc.
2100 Logic Drive
San Jose, CA 95124
Phone: [phone]
Fax:
[phone]
URL: www.xilinx.com
For general Xilinx literature, contact:
Phone:
Email:
408-231-3386 (inside the USA)
408-879-5017 (outside the USA)
[e-mail]
December 5, 2000
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