EP520 Datasheet, PDF (2/3 Pages) List of Unclassifed Manufacturers – EUREKA TECHNOLOGY

EP520 SDRAM Controller
Figure 1: EP520 SDRAM Controller Block Diagram
General Description
The EP520 SDRAM controller interfaces between a pro-
cessor or DMA device with an SDRAM. It performs SDRAM
read and write access based on processor or DMA
requests.
SDRAM timing such as row and column latency, precharge
timing, and row access length are automatically handled by
the SDRAM controller. All these timing parameters are set
by the SDRAM controller on system reset and can be pro-
grammed by the user during run time to optimize system
performance.
The EP520 supports all industry standard SDRAM organi-
zations, ranging from 16Mbit to 256Mbit devices, and from
X4 data width to X16 data width. The user can use multiple
SDRAMs to build access word size from16-bit to 64-bit
wide, or use standard SDRAM DIMMs to build the memory
system. The SDRAM size and word size are programmable
by the memory controller.
Zero wait state data bursting is supported by the SDRAM
controller to maximize data throughput. The back-end inter-
face to user device such as CPU or DMA controller is a
standard microprocessor bus with wait state control. It can
be optimized easily to meet different application require-
ments.
Functional Description
The EP520 core is partitioned into modules as shown in
Figure 1 and described below
State Machine
Based on the request signals ADS_B and CE_B, the state
machine sends control signals to the Counters, Address
Mux, and SDRAM control blocks to access to SDRAM.
READY_B is asserted for each read data that is returned
from the SDRAMs, or for each data that is written to the
SDRAMs. If an access to the Control Registers block is
requested on the CR_ADS_B input, the State Machine
sends appropriate control signals to the Control Registers
block to perform a register write.
SDRAM Control
The SDRAM control block generates the CS_B, CAS_B,
RAS_B and WE_B signals and drives the appropriate
address and DQM[7:0] at the proper timing.
Counters
Under the control of the state machine, the counters keep
track of the burst length and various SDRAM timing param-
eters, such as RAS_B-to-CAS_B delay, active command-
to-precharge time, etc, so that every command is issued at
the correct timing. These timing parameters are program-
mable through the Control Registers.
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December 5, 2000