CS18LV10245 Datasheet, PDF (3/15 Pages) List of Unclassifed Manufacturers – HIgh Speed Super Low Power SRAM

High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
„ PIN DESCRIPTIONS
Name
Function
A0-A16
These 17 address inputs select one of the 131,072 x 8-bit words in the RAM.
Address Input
/CE
/CE is active LOW and CE2 is active HIGH. Both chip enables must be active
Chip Enable Input when data read from or write to the device. If either chip enable is not active,
CE2
the device is deselected and is in a standby power mode. The DQ pins will be
Chip Enable 2 Input in the high impedance state when the device is deselected.
/WE
Write Enable Input
/OE
Output Enable Input
DQ0-DQ7
Data Input/Output
Ports
Vcc
Gnd
The write enable input is active LOW and controls read and write operations.
With the chip selected, when /WE is HIGH and /OE is LOW, output data will
be present on the DQ pins; when /WE is LOW, the data present on the DQ
pins will be written into the selected memory location.
The output enable input is active LOW. If the output enable is active while the
chip is selected and the write enable is inactive, data will be present on the
DQ pins and they will be enabled. The DQ pins will be in the high impedance
state when /OE is inactive.
These 8 bi-directional ports are used to read data from or write data into the
RAM.
Power Supply
Ground
„ TRUTH TABLE
MODE
/WE /CE CE2 /OE
Not
X
H
X
X
Selected
X
X
L
X
Output
H
L
H
H
Disabled
Read
H
L
H
L
Write
L
L
H
X
DQ0~7
High Z
High Z
D_OUT
D_IN
Vcc Current
I_CCSB, I_CCSB1
I_CC
I_CC
I_CC
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2
P3