CS18LV10245 Datasheet, PDF (11/15 Pages) List of Unclassifed Manufacturers – HIgh Speed Super Low Power SRAM

High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
NOTES:
1. T_AS is measured from the address valid to the beginning of write.
2. The internal write time of the memory is defined by the overlap of /CE and /WE low. All
signals must be active to initiate a write and any one signal can terminate a write by
going inactive. The data input setup and hold timing should be referenced to the second
transition edge of the signal that terminates the write.
3. T_WR is measured from the earlier of /CE or /WE going high or CE2 going low at the end
of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the /CE low transition occurs simultaneously with the /WE low transitions or after the
/WE transition, output remain in a high impedance state.
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2
P 11