FDC37N958FR Datasheet, PDF (226/316 Pages) List of Unclassifed Manufacturers – Notebook I/O Controller with Enhanced Keyboard and System Control

Interrupts
The RTC includes three separate fully-automatic
sources of interrupts to the processor. The
alarm interrupt may be programmed to occur at
rates from one-per-second to one-a-day. The
periodic interrupt may be selected for rates from
half-a-second to 122.070 "s. The update
ended interrupt may be used to indicate to the
program that an update cycle is completed.
Each of these independent interrupts are
described in greater detail in other sections.
The processor program selects which interrupts,
if any, it wishes to receive by writing a "1" to
the appropriate enable bits in Register B. A
"0" in an enable bit prohibits the IRQB port from
being asserted due to that interrupt cause.
When an interrupt event occurs a flag bit is set
to a "1" in Register C. Each of the three
interrupt sources have separate flag bits in
Register C, which are set independent of the
state of the corresponding enable bits in
Register B. The flag bits may be used with or
without enabling the corresponding enable bits.
The flag bits in Register C are cleared (record of
the interrupt event is erased) when Register C is
read. Double latching is included in Register C
to ensure the bits that are set are stable
throughout the read cycle. All bits which are
high when read by the program are cleared,
and new interrupts are held until after the read
cycle. If an interrupt flag is already set
when the interrupt becomes enabled, the IRQB
port is immediately activated, though the
interrupt initiating the event may have occurred
much earlier.
When an interrupt flag bit is set and the
corresponding interrupt-enable bit is also set, the
IRQB port is driven low. IRQB is asserted as
long as at least one of the three interrupt
sources has its flag and enable bits both set.
The IRQF bit in Register C is a "1" whenever the
IRQB port is being driven low.
Frequency Divider
The RTC has 22 binary divider stages following
the clock input. The output of the divider is a 1
MHz signal to the update-cycle logic. The
divider is controlled by the three divider bits
(DV3-DV0) in Register A. As shown in Table 69
the divider control bits can select the operating
mode, or be used to hold the divider chain
reset which allows precision setting of the time.
When the divider chain is changed from reset to
the operating mode, the first update cycle is
one-half second later.
Periodic Interrupt Selection
The periodic interrupt allows the IRQB port to be
triggered from once every 500 ms to once every
122.07 "s. As Table 70 shows, the periodic
interrupt is selected with the RS0-RS3 bits in
Register A. The periodic interrupt is enabled with
the PIE bit in Register B.
SMSC DS – FDC37N958FR
Page 220
Rev. 09/01/99