STC62WV25616 Datasheet, PDF (2/10 Pages) List of Unclassifed Manufacturers – Very Low Power/Voltage CMOS SRAM 256K X 16 bit

STC
STC62WV25616
„ PIN DESCRIPTIONS
Name
A0-A17 Address Input
Function
These 18 address inputs select one of the 262,144 x 16-bit words in the RAM.
CE Chip Enable Input
WE Write Enable Input
OE Output Enable Input
LB and UB Data Byte Control Input
CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
Lower byte and upper byte data input/output control pins.
DQ0 - DQ15 Data Input/Output
Ports
Vcc
These 16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Gnd
Ground
„ TRUTH TABLE
MODE
CE WE OE
Not selected
H
X
X
(Power Down)
X
X
X
Output Disabled
L
L
X
H
X
H
Read
L
H
L
Write
L
L
X
LB UB
X
X
H
H
H
H
X
X
L
L
H
L
L
H
L
L
H
L
L
H
D0~D7
High Z
High Z
High Z
High Z
Dout
High Z
Dout
Din
X
Din
D8~D15
High Z
High Z
High Z
High Z
Dout
Dout
High Z
Din
Din
X
Vcc CURRENT
I , I CCSB CCSB1
I , I CCSB CCSB1
ICC
ICC
ICC
ICC
ICC
ICC
ICC
ICC
R0201-STC62WV25616
2
Revision 2.1
Jan. 2004