GF9105A Datasheet, PDF (2/37 Pages) List of Unclassifed Manufacturers – MultiGENTM GF9105A Component Digital Transcoder

PIN DESCRIPTION
PIN NO.
11, 20, 51, 60, 80,
101, 121, 141, 150
4, 7, 10, 14, 21, 43,
52, 61, 63, 72, 81, 88,
96, 100, 105, 113,
120, 129, 138, 140,
149, 158
147, 148, 151-157,
159, 160, 1, 2
131-137, 139, 142-
146
115-119, 122-128,
130
102-104, 106-112,
114
54, 53, 50-44, 42-39
70-64, 62, 59-55
86-82, 79-73, 71
99-97, 95-89, 87
22
24
25
17
16
18
26
23
27-31
3, 5, 6, 8, 9, 12, 13,
15
19
32
SYMBOL
V_DD
GND
P1_12..0
P2_12..0
P3_12..0
P4_10..0
P5_12..0
P6_12..0
P7_12..0
P8_10..0
SYNC_CB
H_BLANK
DP_EN
H
V
F
CS
R/W
ADDR_4..0
COEFF_PORT_7..0
CLK
TCK
+5 V ±5% power supply.
Ground.
DESCRIPTION
Data Port No. 1: Depending on device configuration, P1_12..0 may operate as an input data port or
an output data port. Note: When HVF output is enabled H is always presented on P1₁₂ regardless
of the state of INPUT/OUTPUT.
Data Port No. 2: Depending on device configuration, P2_12..0 may operate as an input data port or
an output data port. Note: When HVF output is enabled V is always presented on P2₁₂ regardless
of the state of INPUT/OUTPUT.
Data Port No. 3: Depending on device configuration, P3_12..0 may operate as an input data port or
an output data port. Note: When HVF output is enabled F is always presented on P3₁₂ regardless
of the state of INPUT/OUTPUT.
Data Port No. 4: Depending on device configuration, P4_10..0 may operate as an input data port or
an output data port.
Data Port No. 5: Depending on device configuration, P5_12..0 may operate as an input data port or
an output data port.
Data Port No. 6: Depending on device configuration, P6_12..0 may operate as an input data port or
an output data port.
Data Port No. 7: Depending on device configuration, P7_12..0 may operate as an input data port or
an output data port.
Data Port No. 8: Depending on device configuration, P8_10..0 may operate as an input data port or
an output data port.
Synchronization: Control signal input. SYNC_CB is used to synchronize the GF9105A to
the incoming data stream.
Horizontal Blanking: Control signal input. H_BLANK is used to replace portions of the
input data with a user selectable set of blanking levels.
Data Port Enable: Control signal input. DP_EN is used to enable and disable data
ports P1 - P8.
Horizontal: Control signal input. H identifies the horizontal blanking interval for the
output multiplexer.
Vertical: Control signal input. V identifies the vertical blanking interval for the output
multiplexer.
Field: Control signal input. F is used to identify field information for the output
multiplexer.
Chip Select: Host interface control signal input.
Read/Write: Host interface control signal input.
Coefficient Address: Input port to identify which GF9105A device address shall be
written to/read from.
Coefficient Port: Host interface bi-directional data port for Color Space Converter
coefficients, KEY scaler coefficient and device configuration words.
System Clock: All timing information is relative to the rising edge of CLK.
JTAG Test Clock Input: Independent clock signal for JTAG.
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