CS18LV20483 Datasheet, PDF (2/16 Pages) List of Unclassifed Manufacturers – High Speec Super Low Power SRAM

High Speed Super Low Power SRAM
256K-Word By 8 Bit
CS18LV20483
GENERAL DESCRIPTION
The CS18LV20483 is a high performance, high speed, and super low power CMOS Static
Random Access Memory organized as 262,144 words by 8 bits and operates from a wide range of
2.7 to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of 0.50uA and maximum
access time of 55/70ns in 3.0V operation. Easy memory expansion is provided by an active LOW
chip enable inputs (/CE1,CE2) and active LOW output enable (/OE) and three-state output drivers.
The CS18LV20483 has an automatic power down feature, reducing the power consumption
significantly when chip is deselected. The CS18LV20483 is available in JEDEC standard 32-pin
sTSOP (8x13.4 mm), TSOP (8x20mm), TSOP (II) (400mil) and SOP (450 mil) packages.
.
FEATURES
Low operation voltage : 2.7 ~ 3.6V
Ultra low power consumption : 2mAï¼ 1MHz (Max.) operating current
0.50 uA (Typ.) CMOS standby current
High speed access time : 55/70ns (Max.) at Vcc = 3.0V.
Automatic power down when chip is deselected.
Three state outputs and TTL compatible
Data retention supply voltage as low as 1.5V.
Easy expansion with /CE and /OE options.
Product Family
Product Family
Operating
Temp
0~70^oC
CS18LV20483
-40~85^oC
Vcc. Range Speed (ns) Standby (Typ.) Package Type
2.7~3.6
2.7~3.6
55/70
55/70
32 SOP
0.50 uA
(Vcc = 3.0V)
32 STSOP
32 TSOP
32 TSOP (II)
Dice
32 SOP
0.8 uA
(Vcc= 3.0V)
32 STSOP
32 TSOP
32 TSOP (II)
Dice
2
Rev. 1.0
Chiplus reserves the right to change product or specification without notice.