TA7S04 Datasheet, PDF (197/198 Pages) List of Unclassifed Manufacturers – Triscend A7S Configurable System-on-Chip Platform

Triscend A7S Configurable System-on-Chip Product Specification
RESET...........................................................89
Reset Hierarchy ...................................................89
Reset Sideband Signals.......................................90
Reset Control Registers Description ....................90
POWER DOWN MODE.....................................93
Entering power down mode .................................94
Exiting power down mode ....................................94
Power-Down Control Registers Description .........95
SYSTEM INITIALIZATION .................................96
System Initialization .............................................96
Parallel Mode ..................................................... 100
JTAG Initialization .............................................. 101
Size of Initialization Data.................................... 102
VSYS Control and Affects on Initialization ......... 102
What If Initialization Fails? ................................. 103
INTERRUPTS ................................................105
Interrupt Control ................................................. 105
Interrupt Sources................................................ 106
ARM FIQ and IRQ Interrupts.............................. 106
Interrupt Controller Sideband Signals ................ 107
Control Registers Description............................. 108
SYSTEM CONTROL REGISTERS ....................113
Remap and Pause Registers ............................. 113
DEDICATED 16-BIT TIMERS ..........................117
Free-Running Mode ........................................... 117
Periodic Timer Mode ..........................................117
Clock Source and Pre-scaling ............................ 118
Control Registers Description............................. 118
WATCHDOG TIMER ......................................120
Watchdog Registers Memory Map ..................... 121
SERIAL PORTS (UARTS) .............................122
Baud Rate Generation ....................................... 122
Transmitting Data............................................... 123
Receiving Data................................................... 123
UART Sideband Signals .................................... 125
DMA Feature...................................................... 125
Modem Feature and Sideband Control Signals.. 125
Serial Ports Register Memory Map .................... 126
DMA CONTROLLER .....................................134
DMA Interaction with A7S System ..................... 134
DMA Transfer Types .......................................... 136
Transfer Data Widths .........................................136
Automatic Address Generation .......................... 137
Controlling Device-Side DMA Transfers............. 138
Device-to-Memory Handshake........................... 140
Memory-to-Device Handshake........................... 142
DMA Requests ................................................... 143
DMA Acknowledge Cycles ................................. 145
Terminating a Transfer....................................... 146
Direct Mode........................................................ 149
Descriptor Mode................................................. 151
Descriptor Table Format .................................... 152
Clearing a DMA Channel ...................................156
DMA Interrupts ................................................... 156
Cyclic Redundancy Check ................................. 157
DMA/Cache Fill Interaction ................................ 157
DMA Channel 0 Control Registers Description .. 158
DEBUGGING INFRASTRUCTURE ................... 167
IEEE 1149.1 JTAG Interface ..............................167
Full ARM Debugging Support.............................167
Hardware Breakpoint Unit ..................................168
Internal Trace Buffer...........................................169
GLOSSARY ................................................. 169
LIFE SUPPORT POLICY................................ 171
RESOURCES ............................................... 172
Web Sites ...........................................................172
Books .................................................................172
PIN DESCRIPTION ....................................... 173
PINOUT DIAGRAMS AND TABLES ................. 175
Available Packages and Package Codes ...........175
Footprint-Compatibility .......................................175
Available PIOs by Package ................................175
Package Power Dissipation/Thermal
Characteristics....................................................175
208-pin PQFP Package Footprint Diagram ........177
208-pin PQFP Package Pinout Tables ...............178
208-pin PQFP Pins by Type ...............................179
208-pin PQFP Package Mechanical Drawing.....180
208-pin PQFP Package Land Pattern Dimensions181
324-ball BGA Package Footprint Diagram..........182
324-ball BGA Package Pinout Tables ................183
324-ball BGA Package Pins by Type .................184
324-ball BGA Package Mechanical Drawing ......185
ELECTRICAL AND TIMING CHARACTERISTICS 186
Absolute Maximum Ratings................................186
Recommended Operating Conditions/DC
Characteristics....................................................186
A7S SWITCHING CHARACTERISTIC GUIDELINES
.................................................................. 187
General A7S Timing Characteristics ..................187
JTAG Interface Timing Characteristics ...............188
SDRAM Interface Timing Characteristics ...........189
Pin-to-Pin Guaranteed Timing Specifications .....192
Memory Interface Unit (MIU) Timing Characteristics195
Asynchronous Memory Interface Timing ............198
Configurable System Interconnect (CSI) Socket
Timing Guidelines...............................................199
Sideband Signal Timing Characteristics .............204
Configurable System Logic (CSL) Cell
(Combinatorial Logic Mode, Sequential Mode)...205
Configurable System Logic (CSL) Cell (Arithmetic
Mode) .................................................................207
Configurable System Logic (CSL) Cell (Memory
Mode, Single-Port RAM).....................................208
Configurable System Logic (CSL) Cell (Memory
Mode, Dual-Port RAM) .......................................210
Configurable System Logic (CSL) Cell (Memory
Mode, 8-bit Shift Register)..................................211
Bus Clock and Global Buffers.............................212
Programmable Input/Output (PIO) Timing
Guidelines ..........................................................213
POWER CONSUMPTION CHARACTERISTICS .. 215
Typical Dynamic Current Consumption Estimates215
Typical Power-Down Mode Current Consumption
Estimates............................................................215
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