LM3S101 Datasheet, PDF (193/284 Pages) List of Unclassifed Manufacturers – Microcontroller

Universal Asynchronous Receiver/Transmitter (UART)
Register 3: UART Flag (UARTFR), offset 0x018
The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and
TXFE and RXFE bits are 1.
UART Flag (UARTFR)
Offset 0x018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
TXFE RXFF TXFF RXFE BUSY
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
Bit
Name
31:8 reserved
7
TXFE
6
RXFF
5
TXFF
Type
RO
RO
RO
RO
Reset
0
1
0
0
Description
Reserved bits return an indeterminate value, and should never
be changed.
UART Transmit FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the transmit holding
register is empty.
If the FIFO is enabled, this bit is set when the transmit FIFO is
empty.
UART Receive FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding
register is full.
If the FIFO is enabled, this bit is set when the receive FIFO is
full.
UART Transmit FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the transmit holding
register is full.
If the FIFO is enabled, this bit is set when the transmit FIFO is
full.
193
March 22, 2006
Preliminary