LM3S101 Datasheet, PDF (10/284 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S101 Data Sheet
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Watchdog Interrupt Clear (WDTICR), offset 0x000 .............................................................. 166
Watchdog Raw Interrupt Status (WDTRIS), offset 0x010..................................................... 167
Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................... 168
Watchdog Lock (WDTLOCK), offset 0xC00.......................................................................... 169
Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 .................................. 170
Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 .................................. 171
Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 .................................. 172
Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC.................................. 173
Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 .................................. 174
Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 .................................. 175
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 .................................. 176
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC.................................. 177
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 ..................................... 178
Watchdog PrimeCell Identification 1(WDTPCellID1), offset 0xFF4 ...................................... 179
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 ..................................... 180
Watchdog PrimeCell Identification 3 (WDTPCellID0), offset 0xFFC..................................... 181
Universal Asynchronous Receiver/Transmitter (UART) ........................................................... 182
Register 1: UART Data (UARTDR), offset 0x000.................................................................................... 189
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004............................ 191
Register 3: UART Flag (UARTFR), offset 0x018..................................................................................... 193
Register 4: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 .............................................. 195
Register 5: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028......................................... 196
Register 6: UART Line Control (UARTLCRH), offset 0x02C................................................................... 197
Register 7: UART Control (UARTCTL), offset 0x030 .............................................................................. 199
Register 8: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034.............................................. 200
Register 9: UART Interrupt Mask (UARTIM), offset 0x038 ..................................................................... 201
Register 10: UART Raw Interrupt Status (UARTRIS), offset 0x03C ......................................................... 203
Register 11: UART Masked Interrupt Status (UARTMIS), offset 0x040.................................................... 204
Register 12: UART Interrupt Clear (UARTICR), offset 0x044 ................................................................... 205
Register 13: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ....................................... 206
Register 14: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ....................................... 207
Register 15: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ....................................... 208
Register 16: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ...................................... 209
Register 17: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ....................................... 210
Register 18: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ....................................... 211
Register 19: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ....................................... 212
Register 20: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC....................................... 213
Register 21: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 .......................................... 214
Register 22: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 .......................................... 215
Register 23: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 .......................................... 216
Register 24: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ......................................... 217
Synchronous Serial Interface (SSI) ............................................................................................. 218
Register 1: SSI Control 0 (SSICR0), offset 0x000................................................................................... 229
Register 2: SSI Control 1 (SSICR1), offset 0x004................................................................................... 231
Register 3: SSI Data (SSIDR), offset 0x008............................................................................................ 232
Register 4: SSI Status (SSISR), offset 0x00C......................................................................................... 233
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 ...................................................................... 234
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ............................................................................. 235
March 22, 2006
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