STAC9460 Datasheet, PDF (14/21 Pages) List of Unclassifed Manufacturers – Two and Six-Channel, 24-Bit, 192 kHz Audio Codec

PRELIMINARY INFORMATION 8/24/01
STAC9460/62
Two and Six-Channel, 24-Bit, 192 kHz Audio Codec
7.1. List of Registers
7.1.1.
Reset/Status Register (00h)
Writing any value to this register performs a register reset, which causes all regis-
ters to revert to their default values. Reading this register returns the corresponding
status of the chip section represented by the bits. The bits are defined below:
BIT
D0
D1
D2
D3-D7
NAME
MIC
DIFF
REF
RESERVED
DESCRIPTION
Microphone inputs
Differential inputs
Reference
RESERVED
Table 5. Reset/Status Register
7.1.2.
Status Register (01h)
Reading this (read only) register returns the corresponding status of the chip section
represented by the bits. The bits are defined below:
BIT NAME
DESCRIPTION
D0
LF
Left front channel
D1
RF
Right front channel
D2
LR
Left rear channel
D3
RR
Right rear channel
D4
CTR Center channel
D5
LFE Low Frequency Effects Channel
D6
AL
Left ADC
D7
AR
Right ADC
Table 6. Status Register
7.1.3.
Master Volume Register (02h)
This register manages the output signal volume for all channels simultaneously and
adds to the individual channel volume registers. The DAC range is from 0 to –96 dB
with each step equivalent to approximately 0.75 dB. The MSB, bit D7, of the regis-
ter is the mute bit for all DACs. When this bit is set, the output level is -∞ dB. Bits
MV6.. MV0 are used to control the master volume.
MMUTE
0
0
1
MV6…MV0
000 0000
111 1111
xxx xxxx
FUNCTION
0 dB Attenuation
96 dB Attenuation
∞ dB Attenuation
Table 7. Master Volume Register
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