STAC9460 Datasheet, PDF (11/21 Pages) List of Unclassifed Manufacturers – Two and Six-Channel, 24-Bit, 192 kHz Audio Codec

PRELIMINARY INFORMATION 8/24/01
STAC9460/62
Two and Six-Channel, 24-Bit, 192 kHz Audio Codec
6.2. Single Line Format
LRCK
SCLK
Left Channel
Right Channel
SDIN 1/2/3
SDATA_OUT
M
S -1
B
L
+1 S
B
M
S -1
B
LM
+1 S S -1
BB
L
+1 S
B
Front
Rear
Center
M
S -1
B
LM
+1 S S -1
BB
LM
+1 S S -1
BB
Front
Rear
Figure 7. Single Line 20 Bit Data Mode Timing Diagram
L
+1 S
B
Bass
Bits/Sample
20
SCLK Rate
128 Fs
Notes
6 inputs, 2 outputs, BRM only
Table 2. Single Line 20 Bit Data Mode, Data Valid on Rising Edge of SCLK
The Single line data mode for the STAC9460 allows data all six channels to be input to the
chip on a single SDATA_IN line, SD1 (Pin 15) and output to all six analog outs (Pins 23-
28). The ADC data will be valid during the first 20 SCLK cycles following a D_LRCLK tran-
sition.
6.3.
I²C-Bus Interface
The I²C-Bus of the STAC9460 operates in compliance with the I²C-Bus Interface Specifi-
cation from Philips Semiconductor. The I²C-Bus for the STAC9460 does include an Auto-
Increment feature not identified by the Phillips specification. For Example, a typical write
would have the following format: START....Chip Address (8 bits)....Register Address(8
bits)....Data(Register Address 8 bits)....Data (Register Address +1 8 bits)....Data (Register
Address +2 8 bits)....STOP. The addresses will increment through the end of the address
space or until a "STOP" condition (as per I²C spec) is received by the part. For detailed
information relating to the I²C, please reference the I²C-Bus Interface Specification from
Philips Semiconductor. Additional information for the Address Registers can be found in
section 7.1.12
Stop Start
Repeated
Start
Stop
SDA
t_buf
t_hdst
t_high
t_hdst
t_f
t_susp
SCL
t_low
t_hdd
t_sud
t_sust
t_r
Figure 8. I²C Timing Diagram
2-9460-D1-1-0-0801
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