STP2200ABGA Datasheet, PDF (1/36 Pages) List of Unclassifed Manufacturers – Uniprocessor System Controller

DATA SHEET
STP2200ABGA
July 1997
USC
Uniprocessor System Controller
DESCRIPTION
The Uniprocessor System Controller (USC) has a DRAM memory controller and functions to regulate the
flow of requests and data on the UPA bus. It also controls the resets going to all UPA clients.
Features
• Controls up to eight standard SS-10/SS-20-type DRAM
SIMMs
• Supports various memory SIMM organizations: 16 MB, 64
MB, and 256 MB as well as dual-stacked 128-MB SIMMs
• Controls and generates a number of resets for the system
• Programmed via a standard 8-bit asynchronous interface
(EBus)
• JTAG interface allows full chip scan
• 225-pin ABGA package
Benefits
• Standard workstation memory
• Flexibility
• High integration
• Allows design of low-cost, low-chip-count embedded
systems
• Ease of design and testability
• Low cost
The USC is used as the system controller of a complete Uniprocessor UltraSPARC system.
Note: Instead of using the U2S, the USC can also be used with the UPA to PCI-bus; I/O interface
controller (U2P)
UPA Devices
USC
RIC
U2S
U2P
XBI
Abbreviations
SC_UP
RISC
SYSIO
Psycho
BMX
Part Number
STP 2200ABGA
STP2210QFP
STP2220ABGA
STP2222ABGA
STP2230SOP
Description
Uniprocessor System Controller
Reset/Interrupt/Clock Controller
UPA to SBus I/O interface controller
UPA to PCI bus I/O Interface controller
Crossbar Data Path
Note: This data sheet refers to the UPA to System I/O interface. The UPA to PCI bus Interface controller
(U2P) can be substituted where U2S appears.
1