CFK2162-P3 Datasheet, PDF (1/4 Pages) List of Unclassifed Manufacturers – 1.8 to 2.0 GHz +34 dBm Power GaAs FET

CFK2162-P3
Product Specifications
July 1997
(1 of 4)
1.8 to 2.0 GHz
+34 dBm Power GaAs FET
Features
t High Gain
t +34 dBm Power Output
t Proprietary Power FET Process
t >45% Linear Power Added Efficiency
t +29 dBm with 30 dBc Third Order Products
t Surface Mount SO-8 Power Package
Applications
t PCS/PCN Base Stations and Terminals
t Wireless Local Loop
Description
The CFK2162-P3 is a high-gain FET intended for dri-
ver amplifier applications in high-power systems, and output
stage usage in medium power applications at power levels up to
+34 dBm. The device is easily matched and provides excellent
linearity at 2 Watts. Manufactured in Celeritek’s proprietary
Package Diagram
GND G G GND
1234
Back Plane
is Source
8 765
GND D D GND
power FET process, this device is assembled in an industry
standard surface mount SO-8 power package that is compatible
with high volume, automated board assembly techniques.
Specifications (TA = 25°C) The following specifications are
guaranteed at room temperature in Celeritek test fixture at 1.95 GHz.
Parameters Conditions
Vd = 8V, Id = 800 mA (Quiescent)
P-1dB
SSG
3rd Order
Products ⁽¹⁾
Efficiency @ P1dB
Vd = 5V, Id = 350 mA (Quiescent)
P-1dB
SSG
Min Typ Max Units
33.0 34.0 — dBm
13.0 14.0 — dB
26 30 — dBc
— 43 — %
— 30.0 — dBm
— 11.0 — dB
Vd = 5V, Id = 1200 mA (Quiescent)
P-1dB
SSG
— 32.5 — dBm
— 12.0 — dB
Absolute Maximum Ratings
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current
Continuous Dissipation
Channel Temperature
Storage Temperature
Symbol
VDS
VGS
IDS
PT
TCH
TSTG
Rating
12V ⁽³⁾
-5V
Idss
10W
175°C
-65°C to +175°C
SO-8 Power Package Physical Dimensions
Parameters
gm
Idss
Vp
BVGD (3)
Θ_JL (2)
Conditions
Vds = 2.0V, Vgs = 0V
Vds = 2.0V, Vgs = 0V
Vds = 3.0V, Ids = 65 mA
Igd = 6.5 mA
@150°C TCH
Min Typ Max
— 1700 —
— 2.8 —
— -1.8
18 20 —
— 10 —
Units
mS
A
Volts
Volts
°C/W
Notes:
1. Sum to two tones with 1 MHz spacing = 29 dBm.
2. See thermal considerations information on page 4.
3. Max (+Vd) and (-Vg) under linear operation. Max potential difference
across the device in RF compression (2Vd + |-Vg|) not to exceed the mini-
mum breakdown voltage (Vbr) of +18V.
3236 Scott Boulevard
Santa Clara, California 95054
Phone: [phone]
Fax: [phone]