FX489 Datasheet, PDF (9/12 Pages) List of Unclassifed Manufacturers – GMSK Modem

Application Information ......
Tx Signal Path Description
The binary data applied to the ‘Tx Data’ input is
retimed within the chip on each rising edge of the ‘Tx
Clock’ and then converted to a 1-volt peak-to-peak
binary signal centred about V_BIAS.
If the ‘Tx Enable’ input is ‘high,’ then this internal
binary signal will be connected to the input of the
lowpass Tx Filter, and the output of the filter connected
to the ‘Tx Out’ pin.
Tx Enable
‘1’ (high)
“0” (low)
Tx Filter Input
1 volt p-p Data In
V
BIAS
Tx Out Pin
Filtered Data
V
BIAS
via
500kΩ
A ‘low’ input to the ‘Tx Enable’ will connect the input of
the Tx Filter to V , and disconnect the ‘Tx Out’ pin
BIAS
from the filter, connecting it instead to V_BIAS through a
high resistance (nominally 500kΩ).
The Tx Filter has a lowpass frequency response,
which is approximately gaussian in shape as shown in
Figure 9, to minimise amplitude and phase distortion of
the binary signal while providing sufficient attenuation
of the high frequency-components which would
otherwise cause interference into adjacent radio
channels. The actual filter bandwidth to be used in any
particular application will be determined by the overall
system requirements. The attenuation-vs-frequency
response of the transmit filtering provided by the
FX489 have been designed to meet the specifications
for most GMSK modem systems, having a -3dB
bandwidth switchable between 0.3 and 0.5 times the
data bit-rate (BT).
Note that an external RC network is required
between the ‘Tx Out’ pin and the input to the
Frequency Modulator (see Figures 2 and 3). This
network, which can form part of any d.c. level shifting
and gain adjustment circuitry, forms an important part
of the transmit signal filtering, and the ground
connection to the capacitor C₁ should be positioned to
give maximum attenuation of high-frequency noise into
the modulator.
The component values should be chosen so that
the product of the resistance (Ohms) and the
capacitance (Farads) is:
BT of 0.3 = 0.34/bit rate (bits/second)
BT of 0.5 = 0.22/bit rate (bits/second)
with suitable values for common bit rates being:
8000 bits/sec, BT = 0.3
4800 bits/sec, BT = 0.5
9600 bits/sec, BT = 0.5
R
91.0kΩ
100kΩ
47.0kΩ
C
470pF
470pF
470pF
The signal at ‘Tx Out’ is centred around V , going
BIAS
positive for logic “1” (high) level inputs to the ‘Tx Data’
input and negative for logic “0” (low) inputs.
When the transmit circuits are put into a
‘powersave’ mode (by a logic “1” to the ‘Tx PS’ pin) the
output voltage of the Tx Filter will go to V_SS.
When power is subsequently restored to the Tx Filter,
its output will take several bit-times to settle. The ‘Tx
Enable’ input can be used to prevent these abnormal
voltages from appearing at the ‘Tx Out’ pin.
Tx Clock
Tx Data
1 BIT PERIOD
Tx DATA SAMPLED BY
THE FX489 AT THESE
INSTANCES
1.0µS Min.
Tx CLOCK AND Rx CLOCK OUTPUTS
(MARK/SPACE) DUTY CYCLE NOMINALLY 50%
1.0µS Min.
DON’T CARE
DATA MUST
BE VALID
Rx Data
Rx Clock
1.0µS Max.
EXTERNAL CIRCUITS SHOULD
SAMPLE Rx DATA AT THIS TIME
Fig.8 Rx and Tx Clock Data Timings
1.0µS Max.
9
DATA INVALID
DATA VALID