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DM8108 Datasheet, PDF (9/35 Pages) List of Unclassifed Manufacturers – 8 port 10/100M Fast Ethernet Switching Controller
99 – 96
115 - 112
137 - 128
127,111,95,79,
60,44,28,12
124,108,92,76,
57,41,25,9
123,107,91,75,
56,40,24,8
126,110,94,78,
59,43,27,11
125,109,93,77,
58,42,26,10
RXD5(3:0)
RXD6(3:0)
RXD7(3:0)
RXCLK(7:0)
RXDV(7:0)
RXER(7:0)
CRS(7:0)
COL(7:0)
72
MDCLK
73
MDIO
DM8108
8 port 10/100M Fast Ethernet Switching Controller
I Receive data for port 5; synchronous to RXCLK5.
I Receive data for port 6; synchronous to RXCLK6.
I Receive data for port 7; synchronous to RXCLK7.
I Receive clock for port 7 – 0; synchronous to RXD, RXDV,RXER; has
same clock rate as TXCLK.
I Receive data valid indication for port 7 – 0.
I Receive data error indication for port 7 – 0.
I Carrier sense; active high. Indicates that either the transmit or
receive medium is not Idle. CRS is not synchronous to any clock.
I Collision Detect; active high. Indicates a collision has been detected
on the wire.
This input is ignored during full duplex operation and in the half duplex
mode while TXEN of the same port is low.
I/O Serial MII management interface clock signal: 1MHz clock for MDIO
data reference. Connected to all PHY ports; It is an input pin if the
device # is not 0 in SDRAM mode; else, it is an output pin.
I/O Serial MII management interface data; this bi-direction line is used to
transfer control Information and status between the PHY and the
DM8108. It conforms to the IEEE-802.3 specifications.
This signal may be connected to the PHY devices of all ports.
Pulled down if not used.
Miscellaneous Interface pins
Pin No.
175
5
6
Pin Name
SCLK
RST*
TESTEN*
I/O
Description
I Memory clock: used by the DRAM state machine.
I Reset signal for the chip.
I Test pin to enable test functions
Power pins
Pin No.
23,55,90,122,
156,185,198
1,7,39,71,74,
106,138,147,
165,174,176,
181,190,196,
203
Pin Name
VCC
GND
I/O
Description
Power Connected to 3.3V Power plane
Ground Connected to Ground plane
Preliminary
9
Version: DM8108-DS-P02
November 25, 1999