AT2008 Datasheet, PDF (9/19 Pages) List of Unclassifed Manufacturers – 8 Channels ADPCM Processor

AT2008
8 Channels ADPCM Processor
Per Channel Control Command Sequence
The Per Channel Control command sequence allows the user to specify some parameters for each half channel. The command sequence
length is variable, and is dependent on the number of channels that are specified. The format of the command consists of a header, a begin
channel number byte, and a data portion containing information of each channel. The total number of bytes in the command sequence
will be 2+2N where N = number of half channels specified.
Below is a sample of Per Channel Control command sequence for two half channels.
Command Byte [7:0]
Description
001
1
0
0 A1 A0 Per Channel Control command Header with A1, A0 chip ID
Channel Configuration Begin
To begin on first channel, set to 0
High Byte 0 0 0
0
0
0 0 0 Configuration for channel 0
Ch0
Low Byte 0 0 0 ADPCM ADPCM LawA 0 Idle
Reset Bypass
High Byte
00
0
0
0 0 0 Configuration for channel 1
Ch1
0
Low Byte 0 0 0 ADPCM ADPCM LawA 0 Idle
Reset Bypass
Note: The format of each data fields like ADPCM reset, ADPCM bypass, lawA, lawP and idle are specified below.
ADPCM Description
reset
0
Normal operation without reset of ADPCM
1
Reset ADPCM internal states
Default: 1
When ADPCM reset bit is ‘1’, ADPCM encoder will output “ff”, ADPCM decoder will output “ff” for u-law and “d5 ” for A-law.
ADPCM Description
bypass
0
Normal operation with ADPCM
1
Bypass ADPCM
Default: 0
LawA Description
0 u-law
1 A-law
Default: 0
Idle Description
0 Normal operation
1 The output is tri-state during its time slot. Once this bit is cleared, it will
come back to normal operation
Default: 0
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©2001 Atelic Systems, Inc.