AT2008 Datasheet, PDF (2/19 Pages) List of Unclassifed Manufacturers – 8 Channels ADPCM Processor

PIN Description
AT2008
8 Channels ADPCM Processor
PIN SYMBOL
16 XIN
20 XOUT
27 YIN
25 FSY
24 YOUT
2
RSTZ
13 XTAL1/MCLK
12 XTAL2
17 CLKP
26 CLKA
18 SYNC1
15 SYNC2
11 SYNC3
10 SYNC4
9
SYNC5
8
SYNC6
5
SYNC7
1
SYNC8
4
TM1
3
TM0
7
A1
6
A0
22 SDI/SDO
21 SCLK
23 SCSZ
28 VDD
14 Vss1
19 Vss2
TYPE
I
O
I
I/O
O
I
I
O
I/O
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I/O
I
I
-
-
-
DESCRIPTION
X Channel Data In. Sampled on the falling edge of CLKP during
selected time slots with MSB first.
X Channel Data Out. Updated on the rising edge of CLKP during
selected time slots with MSB first.
Y Channel Data In. Sampled on the falling edge of CLKA during
selected time slots with MSB first.
Y Channel Frame Sync. Master Y Channel Frame Sync. Signal
followed by the first time slot of transmission. It can be either
input or output by initial setup sequence.
Y Channel Data Out. Updated on the rising edge of CLKA
during selected time slots with MSB first.
Reset. Low active signal to force chip reset.
Crystal In & Out. 14.318 MHz Crystal connected∗∗∗.
PCM Clock. It can be either input created by external control
circuit, or output generated by internal control circuit.
ADPCM Clock. It can be either input created by external control
circuit, or output generated by internal control circuit.
Sync 1. Frame sync. for 1^st CODEC.
Sync 2. Frame sync. for 2^nd CODEC.
Sync 3. Frame sync. for 3^rd CODEC.
Sync 4. Frame sync. for 4^th CODEC.
Sync 5. Frame sync. for 5^th CODEC.
Sync 6. Frame sync. for 6^th CODEC.
Sync 7. Frame sync. for 7^th CODEC.
Sync 8. Frame sync. for 8^th CODEC.
TM1 &TM0 . Tie to Ground for normal operation.
A1 & A0. Address ID key for 3-wire serial port. If match, 3-wire
serial port can be enabled for configuration.
Serial Data In. Data for configuration on the fly by 3-wire serial
port. Sampled on the rising edge of SCLK with LSB first.
Serial Data Out. Output data after sending Read Memory
command by 3-wire serial port. Sampled on the rising edge of
SCLK with LSB first.
Serial Clock. Used to write to the 3-wire serial port registers or
output data from 3-wire serial port registers.
Serial Port Chip Select. Low active to enable 3-wire serial port.
Power. 3.3 Volts.
Ground. 0 Volt.
∗∗∗For clock source other than 14.318MHz, please contact Atelic Systems.
Page 2 of 19
©2001 Atelic Systems, Inc.