16CV8-25 Datasheet, PDF (9/10 Pages) List of Unclassifed Manufacturers – CMOS Programmable Electrically Erasable Logic Device

PEEL^TM 16CV8
A. C. Electrical Characteristics
Over the Operating Range 8, 11
Symbol
Parameter
tPD
tOE
tOD
tCO1
tCO2
tCF
tSC
tHC
tCL, tCH
tCP
fMAX1
fMAX2
fMAX3
tAW
tAP
tAR
tRESET
Input⁵ to non-registered output
Input⁵ to output enable⁶
Input⁵ to output disable⁶
Clock to Output
Clock to comb. output delay
via internal registered feedback
Clock to Feedback
Input⁵ or feedback setup to clock
Input⁵ hold after clock
Clock low time, clock high time⁸
Min clock period Ext (tSC + tCO1)
Internal feedback (1/tSC+tCF)¹¹
External Feedback (1/tCP)¹¹
No Feedback (1/tCL+tCH)¹¹
Asynchronous Reset Pulse Width
Input⁵ to Asynchronous Reset
Asynchronous Reset recovery time
Power-on reset time for registers
in clear state
-25
Min Max
25
25
25
15
Unit
ns
ns
ns
ns
35
10
20
0
15
35
28.5
28.5
33.3
25
25
25
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
5
µs
Switching Waveforms
Inputs, I/O,
Registered Feedback,
Synchronous Preset
Clock
Asynchronous
Reset
Registered
Outputs
Combinatorial
Outputs
Notes:
1. Minimum DC input is -0.5V, however, inputs may undershoot to -2.0V for periods less
than 20 ns.
2. VI and VO are not specified for program/verify operation.
3. Test Points for Clock and VCC in tR and tF are referenced at the 10% and 90% levels.
4. I/O pins are 0V and VCC.
5. “Input” refers to an input pin signal.
6. tOE is measured from input transition to VREF±0.1V, TOD is measured from input transi-
tion to VOH-0.1V or VOL+0.1V; VREF=VL.
7. Capacitances are tested on a sample basis.
8. Test conditions assume: signal transition times of 3ns or less from the 10% and 90%
points, timing reference levels of 1.5V (Unless otherwise specified).
9. Test one output at a time for a duration of less than 1 second.
10. ICC for a typical application: This parameter is tested with the device programmed as
an 8-bit Counter.
11. Parameters are not 100% tested. Specifications are based on initial characterization
and are tested after any design process modification that might affect operational fre-
quency.
9
04-02-004I