16CV8-25 Datasheet, PDF (1/10 Pages) List of Unclassifed Manufacturers – CMOS Programmable Electrically Erasable Logic Device

Commercial
CMOS ProgrammabPlEeEELle™ct1ri6cCalVly8 E-2r5asable Logic Device
Features
• Compatible with Popular 16V8 Devices
- 16V8 socket and function compatible
- Programs with standard 16V8 JEDEC file
- 20-pin DIP, SOIC, TSSOP, and PLCC
• CMOS Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
• Application Versatility
- Replaces random logic
- Super sets standard 20-pin PLDs (PALs)
• Multiple Speed, Power Options
- Speeds range 25ns
- Power as low as 37mA @ 25mHZ
• Development / Programmer Support
- Third party software and programmers
- ICT PLACE Development Software
- Automatic programmer translation and JEDEC file translation
software available for the most popular PAL devices
General Description
The PEEL^TM 16CV8 is a Programmable Electrically Erasable Logic
(PEEL) device providing an attractive alternative to ordinary PLDs. The
PEEL^TM 16CV8 offers the performance, flexibility, ease of design and
production practicality needed by logic designers today.
The PEEL^TM 16CV8 is available in 20-pin DIP, PLCC, SOIC and TSSOP
packages (see Figure 1) with 25ns speed and power consumption as
low as 37mA. EE-Reprogrammability provides the convenience of
instant reprogramming for development and reusable production inven-
tory minimizing the impact of programming changes or errors. EE-
Reprogrammability also improves factory testability, thus assuring the
highest quality possible.
Figure 1 - Pin Configuration
The PEEL^TM 16CV8 architecture allows it to replace over standard 20-
pin PLDs (PAL, GAL, EPLD etc.). See Figure 2. ICT’s PEEL^TM 16CV8
can be programmed with existing 16CV8 JEDEC file. Some program-
mers also allow the PEEL^TM 16CV8 to be programmed directly from
PLD 16L8, 16R4, 16R6 and 16R8 JEDEC files. Additional development
and programming support for the PEEL^TM16CV8 is provided by popular
third-party programmers and development software. ICT also offers free
PLACE development software.
Figure 2 - Block Diagram
I/CLK1
1
20
V_CC
I/CLK1
1
20
V_CC
I
2
19
I/O
I
2
19
I/O
CLK
I
3
18
I/O
I
3
18
I/O
I
4
17
I/O
I
4
17
I/O
/CLK
I
5
I
6
16
I/O
15
I/O
I
5
I
6
I
7
16
I/O
15
I/O
14
I/O
PEEL
"AND"
ARRAY
I
7
I
8
I
9
14
I/O
13
I/O
12
I/O
I
8
I
9
GND
10
13
I/O
12
I/O
11
I
64 TERMS
X
MACRO
CELL
I/O
I/O
I/O
GND
10
11
I
32 INPUTS
I/O
DIP
TSSOP
I/O
I/O
I/O
I/OE
I/O
3 2 1 20 19
I4
18 ^I/O
I5
17 ^I/O
I6
16 ^I/O
I7
15 ^I/O
I8
14 ^I/O
9 10 11 12 13
I/CLK1
1
I
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
GND
10
20
V_CC
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
I/O
12
I/O
11
I
PLCC-J
SOIC
1
04-02-004I