CC2420 Datasheet, PDF (81/87 Pages) List of Unclassifed Manufacturers – 2.4 GHz IEEE 802.15.4 / ZigBee-ready RF Transceiver

SmartRF ^® CC2420
CCAMUX
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Signal output on CCA pin
Description
CCA
Normal operation
ADC_I[0]
ADC, I-branch, LSB used for random number generation
DEMOD_RESYNCH_EARLY
High one 16 MHz clock cycle each time the demodulator
resynchronises early
LOCK_STATUS
Lock status, same as FSCTRL.LOCK_STATUS
MOD_CHIP
Chip rate data signal during transmission
MOD_SERIAL_DATA_OUT
Bit rate data signal during transmission
FFCTRL_FS_PD
Frequency synthesizer power down, active high
FFCTRL_ADC_PD
ADC power down, active high
FFCTRL_VGA_PD
VGA power down, active high
FFCTRL_RXBPF_PD
Receiver bandpass filter power down, active high
FFCTRL_LNAMIX_PD
Receiver LNA / Mixer power down, active high
FFCTRL_PA_P_PD
Power amplifier power down, active high
VGA_PEAK_DET[0]
VGA Peak detector, gain stage 0
VGA_PEAK_DET[2]
VGA Peak detector, gain stage 2
VGA_PEAK_DET[4]
VGA Peak detector, gain stage 4
AGC_LNAMIX_GAINMODE[0]
RF receiver frontend gain mode, bit 0
AGC_VGA_GAIN[0]
VGA gain setting, bit 0
RXBPF_CAL_CLK
Receiver bandpass filter calibration clock
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
PD_F_COMP
Frequency synthesizer frequency comparator value
FSDIG_FREF
Frequency synthesizer, 4 MHz reference signal
FSDIG_FPLL
Frequency synthesizer, 4 MHz divided signal
FSDIG_LOCK_WINDOW
Frequency synthesizer, lock window
WINDOW_SYNC
Frequency synthesizer, synchronized lock window
CLK_ADC_DIG
ADC clock signal 2
ZERO
Low
ONE
High
Table 13. CCA test signal select table
Chipcon AS SmartRF^® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09
Page 81 of 87